Senior Low-Power Wireless SoC Architect

EM Microelectronic; Marin-Epagnier; On-site; CHF 180,000 - 250,000; Full time

Job summary

EM Microelectronic in Neuchâtel is seeking a seasoned Low-Power Wireless SoC Architect to own the digital ASIC architecture from requirements to tape-out. This is a primarily digital design role focusing on processor, memory, power domains, security, and hardware/software partitioning.

The ideal candidate has 12+ years in digital ASIC/SoC design, strong SystemVerilog/Verilog RTL experience, and proven ownership of a low-power SoC from architecture through production.

Qualifications

• Master’s degree in Electrical Engineering or related field; Ph.D. preferred.
• Typically 12+ years in digital ASIC/SoC design, integration, or architecture.
• Strong RTL design experience with SystemVerilog/Verilog and ownership of a low-power SoC.

Responsibilities

• Own the digital SoC architecture: processor, interconnect, memory hierarchy, clock/reset, power domains and modes, peripherals, security, debug, test, and hardware/software partitioning.
• Translate product requirements into architecture specifications, interfaces, verification objectives, and measurable power, performance, area, cost, and risk budgets.
• Drive digital ASIC decisions covering IP selection and reuse, RTL architecture, low-power intent, CDC/RDC, DFT, implementation constraints, and design-for-verification.
• Align Digital Design, Verification, IC Integration, software, validation, test, memory, analog/RF, CAD/PDK, package, and manufacturing contributors.
• Lead architecture reviews and formal change control; support implementation, tape-out, silicon bring-up, qualification, yield improvement, and production issue resolution.

Skills

SystemVerilog

RTL design

Low-power design

Architecture leadership

Security

Education

Master’s degree in Electrical Engineering

Ph.D. preferred

Tools

EDA tools

Job description

EM Microelectronic in Neuchâtel is seeking a seasoned Low-Power Wireless SoC Architect to own the digital ASIC architecture from requirements to tape-out. This is a primarily digital design role focusing on processor, memory, power domains, security, and hardware/software partitioning.

The ideal candidate has 12+ years in digital ASIC/SoC design, strong SystemVerilog/Verilog RTL experience, and proven ownership of a low-power SoC from architecture through production.