Senior FPGA Engineer — Test Automation & Amaranth

Michael Page International (Switzerland) SA; Lausanne; Vor Ort; CHF 120.000 - 150.000; Vollzeit

Zusammenfassung

Michael Page International (Switzerland) SA is seeking an experienced FPGA engineer to design and implement firmware for automated test systems. You will work with Amaranth, Yosys and other frameworks while supporting test automation and verification environments.

You will develop Python-based tools, contribute to CI/CD pipelines and collaborate with software, hardware, and test teams. A strong background in Verilog/VHDL and hands-on FPGA experience are essential, with English fluency and Swiss

Qualifikationen

• 5+ years of FPGA development experience.
• Bachelor's or Master's degree in Electronics, Computer Engineering, Computer Science, or a related field.
• Strong knowledge of FPGA design using Verilog and/or VHDL.
• Hands-on experience with FPGA design frameworks such as Amaranth, Yosys, LiteX, Migen, MyHDL, or Chisel.
• Strong programming skills in Python.
• Experience with FPGA simulation and verification tools such as Verilator, Icarus Verilog, or GTKWave.
• Familiarity with Git, GitHub Actions, Docker, and CI/CD environments.
• Excellent communication skills in English; French is a plus.
• You MUST be eligible to work in Switzerland.

Aufgaben

• Design and develop FPGA firmware for automated test systems.
• Contribute to the development of a test automation framework.
• Implement and validate FPGA modules supporting integration and qualification testing.
• Develop reusable and maintainable FPGA architectures.
• Utilize modern FPGA design frameworks such as Amaranth and related technologies.
• Create simulation environments and verification testbenches.
• Develop Python-based tools and scripts for automation and validation.
• Analyze test results and troubleshoot hardware and firmware issues.
• Collaborate closely with software, hardware, and test engineering teams.
• Follow structured development processes and contribute to continuous improvement initiatives.
• Support CI/CD workflows and engineering automation activities.
• Document designs, verification activities, and technical decisions.

Kenntnisse

FPGA development

Verilog/VHDL

Python

Git/GitHub Actions

CI/CD

English communication

French (nice to have)

Ausbildung

Bachelor's or Master's in Electronics/CS/related

Tools

Amaranth

Yosys

LiteX

Migen

MyHDL

Chisel

Verilator

GTKWave

Icarus Verilog

Jobbeschreibung

Michael Page International (Switzerland) SA is seeking an experienced FPGA engineer to design and implement firmware for automated test systems. You will work with Amaranth, Yosys and other frameworks while supporting test automation and verification environments.

You will develop Python-based tools, contribute to CI/CD pipelines and collaborate with software, hardware, and test teams. A strong background in Verilog/VHDL and hands-on FPGA experience are essential, with English fluency and Swiss