Senior DFT Engineer for High-Speed ASIC/SoC Testing

Intellectual Capital Resources Ltd; Lausanne; On-site; CHF 90,000 - 130,000; Full time

Job summary

Intellectual Capital Resources Ltd is seeking a DFT Engineer to join a leading semiconductor team in Lausanne, Switzerland (or the UK). You will work across DFT implementation, test pattern development, timing, simulation and silicon bring-up with hands-on engagement on complex designs.

The role involves MBIST, scan insertion, boundary scan, ATPG, and IJTAG methodologies, developing patterns and debugging timing-aware simulations to ensure robust production tests.

Qualifications

• 5+ years of experience in DFT.
• Experience across DFT implementation, test pattern development and simulation.
• Experience contributing to DFT solutions for complex ASIC or SoC designs.
• Strong knowledge of IJTAG methodologies.
• Experience with hierarchical MBIST insertion and scan compression.
• Strong ATPG experience across fault models.
• Experience analysing fault coverage and driving coverage closure.
• Strong debugging skills, timing-aware pattern simulation.
• Experience with industry-standard EDA tools for DFT, timing and simulation.
• Good scripting skills for automation.
• Knowledge of SystemVerilog.

Responsibilities

• Hierarchical MBIST and scan insertion, including scan compression.
• Boundary Scan Design (BSD) implementation.
• ATPG pattern generation, coverage analysis, driving high coverage.
• Running and debugging pattern simulations with timing.
• Defining test-mode timing constraints and analysing timing reports.
• Supporting timing convergence across test modes.
• Developing cycle-accurate functional patterns using IJTAG.
• Collaborating with test and production engineering during probe and final test.
• Supporting device bring-up and debugging silicon issues.
• Developing scripts and automation to improve DFT flows.

Skills

Scripting for automation

Debugging skills

SystemVerilog knowledge

IJTAG methodologies

Pattern generation

Education

Bachelor’s degree or higher in Electronics or related field

Tools

MBIST

Scan insertion

ATPG

Job description

Intellectual Capital Resources Ltd is seeking a DFT Engineer to join a leading semiconductor team in Lausanne, Switzerland (or the UK). You will work across DFT implementation, test pattern development, timing, simulation and silicon bring-up with hands-on engagement on complex designs.

The role involves MBIST, scan insertion, boundary scan, ATPG, and IJTAG methodologies, developing patterns and debugging timing-aware simulations to ensure robust production tests.