Senior Design Verification Engineer (PCIe / Serdes / USB / ethernet)

TN Switzerland; Schweiz; Vor Ort; CHF 110’000 - 120’000; Vollzeit

Zusammenfassung

Join a cutting-edge semiconductor company as a Senior Digital Design Verification Engineer. This exciting role involves working on high-speed communication ASIC technologies and collaborating with a talented team on complex R&D projects. You will leverage your expertise in digital verification, coding, and UVM environments to drive innovation in the semiconductor industry. If you have a strong background in electronics and a passion for technology, this is the perfect opportunity to make a significant impact in a dynamic and forward-thinking environment.

Qualifikationen

• University degree in Electronics, Microelectronics, Physics, or Computer Science.
• Industry experience in digital verification for FPGA/ASIC.

Aufgaben

• Work on key R&D projects for complex IP with designers and verification engineers.
• Develop UVM environments and complex test-benches for digital IPs.

Kenntnisse

Digital Verification

VHDL

Verilog

SystemVerilog

Python

C

C++

SystemC

UVM

Ausbildung

BSc in Electronics

MSc in Microelectronics

PhD in Physics

BSc in Computer Science

Tools

Matlab

Simulink

Jasper Gold

OneSpin

Jobbeschreibung

Working for a cutting-edge semiconductor company, I have a brand-new Senior Digital Design Verification opportunity to work on the latest high-speed communication ASIC technologies.

You will be part of key R&D projects for complex IP - working closely with designers, architects, and other verification engineers in the wider business.

Salary: 110-120k CHF

Must have skills:

• University degree - BSc / MSc / PhD in Electronics, Microelectronics, Physics or Computer Science
• Industry experience in digital verification - for FPGA / ASIC (VHDL and / or Verilog, SystemVerilog)
• Good language & communication skills in English
• Strong coding skills - Python / C / C++ / SystemC
• UVM environments, libraries, and complex test-benches for digital IPs

Bonus / "nice-to-have" skills:

• Definition of complex digital architecture
• High-speed digital connectivity and protocols - SerDes, Ethernet, USB, PCIe, AMBA / AXI, MAC, PHY, cache coherency - MESI
• Testing / validation
• Matlab / Simulink modelling experience
• Confident software coding skills - C++ / Python etc
• Formal / software verification - Jasper Gold, OneSpin, SVA - SystemVerilog assertions