Automation & Testing Engineer—RTL/EDA Tools

Google Inc.; Zürich; Vor Ort; CHF 180.000 - 240.000; Vollzeit

Zusammenfassung

Google DeepMind is seeking a Software Engineer for Automated Correctness and Testing to advance RTL generation and hardware compilation tools within EDA workflows. You will design, implement, and optimize software that verifies correctness across simulations and hardware deployments.

The role requires extensive C++, Python, and SystemVerilog experience, collaboration with ML researchers and hardware architects, and a focus on scalable automation for production-quality tooling.

Qualifikationen

• Bachelor's degree in CS or related field, or equivalent practical experience.
• 8 years of experience programming in C++, Java, Python, Kotlin or Go.
• 8 years of experience with SystemVerilog, hardware design, automation, design verification test.
• 3 years of experience with software design and architecture.

Aufgaben

• Design, develop, and optimize software tools to improve the quality of generated RTL and accelerate the execution of hardware compilation and EDA tools.
• Profile, identify, and resolve performance bottlenecks in software tools to speed up optimization and synthesis cycles.
• Collaborate with hardware architects, compiler engineers, and ML researchers to bridge the gap between high-level representations and highly optimized RTL.
• Develop robust, scalable automation scripts and software libraries to streamline and speed up RTL generation and optimization workflows.
• Work with product engineering teams to bring the software tools we are developing to production quality.

Kenntnisse

C++

Java

Python

Kotlin

Go

SystemVerilog

Hardware design

Automation

Design and architecture

Ausbildung

Bachelor's degree in Computer Science or related field

Master’s degree or PhD in Engineering, Computer Science, or related field

Tools

SystemVerilog

Jobbeschreibung

Google DeepMind is seeking a Software Engineer for Automated Correctness and Testing to advance RTL generation and hardware compilation tools within EDA workflows. You will design, implement, and optimize software that verifies correctness across simulations and hardware deployments.

The role requires extensive C++, Python, and SystemVerilog experience, collaboration with ML researchers and hardware architects, and a focus on scalable automation for production-quality tooling.