ASIC Front-End Designer - Open-Source RTL & Tapeout

Physics World; Genf; Hybrid; CHF 63.192 - 69.516; Vollzeit

Benefits dieser Stelle

CHF stipend

30 days leave

Health insurance

Pension scheme

Relocation package

Language training

Zusammenfassung

CERN is seeking a talented engineer to design, simulate, and verify the digital front-end for the next-generation ASICs used in radiation monitoring and safety-critical systems. You will prepare RTL for tapeout, work with open-source EDA tools, and assist after-fabrication bring-up and validation.

Ideal candidates have experience with RTL to GDSII, floorplanning, and hardware debugging. A hybrid work model is offered with opportunities for professional growth within CERN's HSE-TS-IMS division.

Qualifikationen

• Proficient HDL design and simulation (VHDL/Verilog/SystemVerilog).
• Hands-on with open-source ASIC flows from RTL to GDSII.
• Familiar with floorplanning and physical design prep for tapeout.

Aufgaben

• Design, simulate, and verify the digital architecture of the next-generation ASIC front-end.
• Prepare RTL designs for tapeout using open-source flows including floorplanning.
• Support post-fabrication bring-up, system characterization, and validation.
• Collaborate with analogue, verification, and SoC teams for system-level compatibility.

Kenntnisse

HDL design

Git

Python

Linux

Teamwork

English

Ausbildung

Bachelor's or Master's in Electronics or related field

Tools

Yosys

OpenROAD

LibreLane

Jobbeschreibung

CERN is seeking a talented engineer to design, simulate, and verify the digital front-end for the next-generation ASICs used in radiation monitoring and safety-critical systems. You will prepare RTL for tapeout, work with open-source EDA tools, and assist after-fabrication bring-up and validation.

Ideal candidates have experience with RTL to GDSII, floorplanning, and hardware debugging. A hybrid work model is offered with opportunities for professional growth within CERN's HSE-TS-IMS division.