IOMMU Verification Engineer

AMD; Vancouver; On-site; CAD 110,000 - 160,000; Full time

Benefits offered by this job

Benefits at a glance

Job summary

AMD is seeking an ASIC Design Verification Engineer in Vancouver/Markham to join the NBIO team. You will help create verification architectures, define test plans, develop verification environments, and drive verification closure for next-gen I/O connectivity tech powering data centers and AI workloads.

You will own end-to-end verification for key features, work with IP architects, and use SystemVerilog/SVA/UVM to build tests, regressions, and coverage.

Qualifications

• Strong ASIC verification experience is required.
• Strong understanding of digital design and computer architecture.
• Proficient in Verilog, System Verilog, SVA, C/C++, UVM, OOP, and working in Linux and Windows environments.
• ASIC design knowledge and be able to debug System Verilog RTL code using simulation tools.
• Experience in security verification would be an asset.

Responsibilities

• Collaborate with IP architects to develop verification architecture and plans.
• Participate in verification of complex IP blocks and own key features across projects.
• Develop test plans, verification environments, regression suites, and coverage closure.
• Develop and maintain VIP, libraries, and verification environments using SystemVerilog/SVA/UVM.
• Triaging and debugging regressions.
• Analyze code and functional coverage.
• Apply verification methodologies such as UVM and formal verification.
• Reproduce functional bugs in post-silicon or formal environments.
• Conduct and participate in code reviews.
• Develop and maintain scripts and tools to improve engineering infrastructure.

Skills

ASIC verification experience

Digital design

Computer architecture

Debug SystemVerilog

C/C++

UVM

Education

BS/MS in Engineering

Tools

Verilog

SystemVerilog

SVA

Linux

Windows

OOP

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

The AMD IOHUB Team (part of the NBIO organization) is looking for an ASIC Design Verification Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP verification starting from helping to create a verification architecture, defining test plans, verification environment development, and verification closure/sign-off. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to show casesuccesses as well as facilitatecontinuous career development.

THE PERSON:

• Strong analytical thinking and problem-solving skills, excellent attention to detail.
• Possesses good teamwork, communicationand interpersonal skills
• A self-starter and able to independently drive tasks to completion
• Enjoys working in a fast-paced, multi-project team environment using state of the art tools and technology
• Possesses a continuous improvement mind-set

KEY RESPONSIBILITIES:

• Collaborate with IP architects tocome up withverification architecture and development plans
• Participate in verification of complex IP blocks and take end-to-end ownership of key features for all projects
• Work on test plans, verification environment development, regression, and coverage closure
• Develop modifying and maintaining VIP, libraries, verification environments, testcases (random and directed) using System Verilog/SVA/UVM
• Triaging and Debugging Regressions
• Analyzing code and functional coverage
• Deploying industry-leading verification methodologies such as UVM and formal Verification
• Reproducing functional bugs found inPost-Siliconin dynamic simulation and/or formal verification environments
• Conducting andparticipatingin code reviews
• Develop andmaintainscripts and tools to continuously improve in engineering infrastructure,methodologyand execution

PREFERRED EXPERIENCE:

• Strong ASIC verification experience is required
• Strong understanding of digital design and computer architecture
• Proficient in Verilog, System Verilog, SVA, C/C++, UVM, OOP, and working in Linux and Windows environments
• ASIC design knowledge and be able to debug System Verilog RTL code using simulation tools
• Experience in security verification would be an asset

ACADEMIC CREDENTIALS:

• BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science.

LOCATION:

Vancouver, Markham

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.