Technology Lead- Memory Layout

Infosys; Vancouver; On-site; CAD 90,000 - 137,000; Full time

Job summary

Infosys in Vancouver is seeking a Memory Team Layout engineer to join the Registers and Memory Arrays group. You will translate schematics into optimized layout, collaborating with circuit teams to advance memory data-path design.

Strong Cadence Virtuoso and Calibre experience is required, with 3nm/5nm exposure and a Bachelor’s degree. Candidates should have 5+ years in compiler/memory layout design, and be prepared to relocate or commute to Vancouver, BC.

Qualifications

• Bachelor's degree or foreign equivalent; will consider 3 years of progressive experience in lieu of education.

Responsibilities

• Layout and design of Memory Leafs and associated data paths.

Skills

Memory layout design

Compiler experience

Cadence tools

DRC/LVS/ERC

Finfet knowledge

3nm/5nm exposure

Communication skills

Education

Bachelor's degree or foreign equivalent

Tools

Cadence Virtuoso

Calibre

Job description

Infosys is hiring Memory Team Layout. You will work along our Registers and Memory Arrays and Memory data path layout and design engineers .Based on the schematic shared you should be able to take it forward and collaborate with circuit team etc to create best layout possible.

Required Qualifications:

• Candidate must be located within commuting distance of Vancouver BC, Canada or be willing to relocate to the area. This position may require travel in Canada.
• Bachelor’s degree or foreign equivalent required from an accredited institution. Will also consider three years of progressive experience in the specialty in lieu of every year of education.
• At least 4 years of Information Technology experience.
• Candidates authorized to work for any employer in the Canada without employer-based visa sponsorship are welcome to apply. Infosys is unable to provide immigration sponsorship for this role at this time.

Required Skills :

• Minimum Qualifications 5+ years of experience in Compiler/Custom Memory Layout design.
• Memory Leafcell layout library design from scratch including top level integration.
• Good knowledge on diAerent types of memory architectures.
• Good knowledge in optimized layout design for better performance.
• Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.
• 3nm, 5 nm exposure required Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.
• Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow.

The job may also entail sitting as well as working at a computer for extended periods of time. Candidates should be able to effectively communicate by telephone, email, and face to face.

Estimated annual compensation range for the candidate based in the below location will be:

BC- $90450 to $136500

About Us

Infosys is a global leader in next-generation digital services and consulting. We enable clients in more than 50 countries to navigate their digital transformation. With over four decades of experience in managing the systems and workings of global enterprises, we expertly steer our clients through their digital journey. We do it by enabling the enterprise with an AI-powered core that helps prioritize the execution of change. We also empower the business with agile digital at scale to deliver unprecedented levels of performance and customer delight. Our always-on learning agenda drives their continuous improvement through building and transferring digital skills, expertise, and ideas from our innovation ecosystem.

EEO

Infosys provides equal employment opportunities to applicants and employees without regard to race; color; sex; gender identity; sexual orientation; religious practices and observances; national origin; pregnancy, childbirth, or related medical conditions; status as a protected veteran or spouse/family member of a protected veteran; or disability.