Custom Layout Design Engineer

AMD; Markham; On-site; CAD 110,000 - 140,000; Full time

Benefits offered by this job

Benefits at a glance

Collaborative global team

Job summary

AMD is seeking an engineer for the Full Custom IC Layout team to design and implement layouts for digital and analog circuits. You will work on high-speed I/O drivers, delay lines, and clock systems using advanced process nodes, collaborating with global teams to tape out complex blocks.

Role involves floorplanning, routing, verification, and developing robust layout methodologies while leveraging AI-assisted tools to boost productivity and design quality.

Qualifications

• Experience in custom IC layout design.
• Solid understanding of CMOS device theory and circuit fundamentals.
• Experience with LVS, DRC, EM/IR verification and related methodologies.
• Exposure to advanced process nodes (2nm–7nm).
• Experience with IP or standard-cell layouts and high-speed signaling.

Responsibilities

• Create high-quality, manufacturable layouts for digital and analog cells at transistor level using Cadence Virtuoso.
• Floorplan, route, and assemble cells into macros for IP blocks.
• Develop models and tape-out collateral for custom blocks.
• Perform hierarchical verification (DRC, LVS, ERC, EM/IR, latch-up/ESD) and drive issue resolution with designers.
• Explore AI-assisted tools to improve layout productivity and verification efficiency.

Skills

CMOS layout

IC design

Digital/Analog layout

Scripting/automation

Cross-functional collaboration

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence Virtuoso

Calibre

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou'redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger- technologythat moves the world forward.Join us and, together, we'll advance your career.

THE ROLE:

The Full Custom IC Layout team is seeking an engineer to design and implement layouts for digital and analog circuits based on schematics using industry-standard CAD tools and advanced semiconductor process technologies. Examples of layouts developed by our team include high-speed I/O drivers and receivers, delay lines, duty-cycle correction (DCC) circuits, calibration circuits, clock buffers, and custom digital circuits.

This team plays a critical role in enabling AMD's next-generation semiconductor products. Team members collaborate across multiple engineering disciplines to solve complex technical challenges and contribute to innovative solutions used by customers worldwide. In this role, you will have the opportunity to work on impactful technologies while developing expertise in advanced process nodes, custom layout methodologies, and physical design verification.

THE PERSON:

In this role, you will contribute across multiple phases of the design lifecycle, from initial floor planning and routing of lower-level logic gates through top-level integration, verification, and tape out activities. Day-to-day responsibilities include creating lower-level cell layouts and assembling them into larger IP blocks. You will use a variety of verification tools throughout the design hierarchy, including DRC, LVS, EM/IR, ERC, and Latch-up/ESD verification. As you grow in the role, you may also collaborate with and help coordinate work across globally distributed engineering teams and external design partners.

KEY RESPONSIBILITIES:

• Create high-quality, manufacturable layouts for digital and analog building blocks at the transistor level using Cadence Virtuoso.
• Floorplan, route, and assemble lower-level cells into macros.
• Build black-box and abstract models consumed by other teams and contribute to tape out collateral for custom blocks.
• Run hierarchical verification at the cell and macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and drive issue resolution in collaboration with circuit designers.
• Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.

PREFERRED EXPERIENCE:

• Experience in custom IC layout design is preferred. Candidates with relevant industry, research, internship, or project experience are encouraged to apply.
• Demonstrated understanding of CMOS device and circuit theory, as well as analog and digital layout best practices.
• Experience using industry-standard layout tools such as Cadence Virtuoso and Calibre.
• Experience with LVS, DRC, EMIR, and other physical verification methodologies.
• Exposure to advanced process nodes (e.g., 2nm, 3nm, 5nm, or 7nm technologies).
• Experience with IP or standard-cell layout, high-speed differential signaling, PLL/DLL/VCO circuits, DACs, power pads, and in-context XOR verification.
• Experience with scripting or automation using Perl, TCL, SVRF/TVF, SKILL, or similar languages is a plus.

ACADEMIC CREDENTIALS:

• Bachelor's or master's degree in Electrical Engineering, Mechanical Engineering, Electronics, or a related technical field.

#LI-DP1

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.

This posting is for an existing vacancy.