System Architect Verification Engineer

RANOVUS Inc.; Ottawa; On-site; CAD 110,000 - 160,000; Full time

Job summary

Ranovus Inc. in Ottawa, ON, Canada is seeking a stem Architect Verification Engineer to validate pre-silicon systems for the optical engine.

You will develop SystemVerilog models, build verification testbenches, and verify closed-loop control algorithms to ensure firmware and ASIC logic correctness before silicon arrives. The role requires 6+ years in digital or mixed-signal verification, with familiarity in RTL tools and optical component concepts.

Qualifications

• S. in Electrical Engineering or related field with 6+ years of experience, or Ph.D. with 3+ years in verification.
• Familiarity with RTL simulation tools.
• Understanding of closed-loop control concepts for PIC components and bring-up sequencing.
• Basic understanding of optical/photonic components such as micro-ring modulators and photodetectors.
• Python or MATLAB for scripting, data analysis, and regression automation.

Responsibilities

• Develop and maintain SystemVerilog behavioral models for PIC, ASIC, and Laser subsystems.
• Build and run control verification testbenches for bring-up sequences and link training.
• Verify closed-loop control algorithms used to calibrate PIC components and wavelength locking.
• Perform RTL-level verification of ASIC control blocks with the ASIC team.
• Develop regression environments for control algorithms and bring-up validation.
• Run corner-case simulations across PVT conditions and aging scenarios.
• Correlate simulation results with lab measurements to validate models.

Skills

SystemVerilog

RTL simulation

Closed-loop control concepts

Python

MATLAB

Education

S. in Electrical Engineering or PhD with related experience

Tools

Verilog-A/Verilog-AMS

SPICE / mixed-signal simulation

Job description

stem Architect Verification Engineer

Ottawa, ON, Canada | Full-Time | Ranovus

About Ranovus

Ranovus is a fabless semiconductor company headquartered in Ottawa, Canada, developing next-generation co-packaged optics (CPO) solutions for AI and data center interconnects. Our Odin optical engine integrates a Quantum Dot Multi-Wavelength Laser, Photonic Integrated Circuit (PIC), and ASIC into a single co-packaged module – delivering the performance and density required by hyperscale AI infrastructure.

About The Role

The System Architect Verification engineer develops and runs behavioral simulations and control verification tests for the optical engine (OE). Working in System Verilog and RTL, you will validate control algorithm, bring-up sequences, and link training algorithms before silicon is available – ensuring firmware and ASIC logic are correct before the first chip arrives.

Key Responsibilities

• Develop and maintain System Verilog behavioral models of PIC, ASIC, and Laser subsystems for pre-silicon system simulation.
• Build and run control verification testbenches: mission mode, bring-up sequences, link training, OE calibration, and fault recovery state machines.
• Verify closed-loop (feedback) control algorithms used to calibrate and stabilize PIC components, such as bias and wavelength locking loops.
• Perform RTL-level verification of ASIC control blocks in collaboration with the ASIC team.
• Develop and maintain regression environments for control algorithm and bring-up validation.
• Run corner case simulations across PVT (process, voltage, temperature) conditions and aging scenarios.
• Correlate simulation results against lab measurements to validate model accuracy.
• Support pre-silicon firmware validation in collaboration with the FW team.
• Extend the system simulation environment as new blocks and features are added.

Required Qualifications

• S. in Electrical Engineering or related field with 6+ years of experience, or Ph.D. with 3+ years of experience, in digital or mixed-signal verification using SystemVerilog.
• Familiarity with RTL simulation tools.
• Understanding of closed-loop (feedback) control concepts for controlling PIC components (e.g., bias/wavelength locking control loops) and hardware bring-up sequencing.
• Basic understanding of optical/photonic components such as micro-ring modulators (MRM), photodetectors, and similar devices.
• Python or MATLAB for scripting, data analysis, and regression automation.

NICE TO HAVE

• Experience with Verilog-A or Verilog-AMS for modeling analog or optical components.
• Experience with optical or photonic system simulation.
• Familiarity with SPICE or mixed-signal analog simulation.
• Understanding of PAM4 link behavior and BER analysis.
• Exposure to SerDes or high-speed interface IP verification.