System Architect Verification Engineer

Ranovus; Ottawa; On-site; CAD 90,000 - 130,000; Full time

Job summary

Ranovus in Ottawa, ON, is seeking a System Architect Verification Engineer to join our pre-silicon verification team. You will develop SystemVerilog models, run control verification testbenches, and validate bring-up sequences for the Odin optical engine.

This role offers exposure to RTL verification, lab correlation, and collaboration with firmware and ASIC teams, with growth into a senior position as silicon arrives.

Qualifications

• BS/MS in Electrical Engineering or related field required.
• 4+ years in digital or mixed-signal verification using SystemVerilog.
• Familiarity with RTL simulation tools (VCS, Xcelium, or ModelSim).
• Understanding of control state machines and hardware bring-up sequencing.
• Python or MATLAB for scripting, data analysis, and regression automation.

Responsibilities

• Develop SystemVerilog behavioral models of PIC, ASIC, and Laser subsystems for pre-silicon system simulation.
• Build and run control verification testbenches: bring-up sequences, link training, OE calibration, fault recovery state machines.
• Perform RTL-level verification of ASIC control blocks in collaboration with the ASIC team.
• Develop and maintain regression environments for control algorithm and bring-up validation.
• Run corner case simulations across PVT conditions and aging scenarios.
• Correlate simulation results against lab measurements to validate model accuracy.
• Support pre-silicon firmware validation in collaboration with the FW team.
• Extend the system simulation environment as new blocks and features are added.

Skills

System Verilog

Hardware verification

Python scripting

Education

B.S. or M.S. in Electrical Engineering

Tools

VCS

Xcelium

ModelSim

Verilog-A

Verilog-AMS

UVM

Job description

System Architect Verification Engineer

Ottawa, ON, Canada | Full-Time | Ranovus

ABOUT RANOVUS

Ranovus is a fabless semiconductor company headquartered in Ottawa, Canada, developing next-generation co-packaged optics (CPO) solutions for AI and data center interconnects. Our Odin optical engine integrates a Quantum Dot Multi-Wavelength Laser, Photonic Integrated Circuit (PIC), and ASIC into a single co-packaged module -- delivering the performance and density required by hyperscale AI infrastructure.

ABOUT THE ROLE

The System Verification Engineer develops and runs behavioral simulations and control verification tests for the Ranovus Odin optical engine. Working in System Verilog and RTL, you will validate control state machines, bring-up sequences, and link training algorithms before silicon is available -- ensuring firmware and ASIC logic are correct before the first chip arrives. This role works closely with the existing verification lead and is an opportunity to grow into a senior position.

KEY RESPONSIBILITIES

• Develop and maintain System Verilog behavioral models of PIC, ASIC, and Laser subsystems for pre-silicon system simulation.
• Build and run control verification testbenches: bring-up sequences, link training, OE calibration, and fault recovery state machines.
• Perform RTL-level verification of ASIC control blocks in collaboration with the ASIC team.
• Develop and maintain regression environments for control algorithm and bring-up validation.
• Run corner case simulations across PVT (process, voltage, temperature) conditions and aging scenarios.
• Correlate simulation results against lab measurements to validate model accuracy.
• Support pre-silicon firmware validation in collaboration with the FW team.
• Extend the system simulation environment as new blocks and features are added.

REQUIRED QUALIFICATIONS

• B.S. or M.S. in Electrical Engineering or related field.
• 4+ years in digital or mixed-signal verification using System Verilog.
• Familiarity with RTL simulation tools (VCS, Xcelium, or ModelSim).
• Understanding of control state machines and hardware bring-up sequencing.
• Python or MATLAB for scripting, data analysis, and regression automation.

NICE TO HAVE

• Experience with Verilog-A or Verilog-AMS for modeling analog or optical components.
• Experience with optical or photonic system simulation.
• UVM (Universal Verification Methodology) background.
• Familiarity with SPICE or mixed-signal analog simulation.
• Understanding of PAM4 link behavior and BER analysis.
• Exposure to SerDes or high-speed interface IP verification.