Staff ASIC Design Engineer

HRB; Canada; Remote; CAD 120,000 - 160,000; Full time

Job summary

A leading company is seeking a Staff ASIC Design Engineer to join their team, contributing to innovative projects in ASIC and FPGA design. This role involves leading design efforts, ensuring the application of best practices, and mentoring junior engineers in a fast-paced environment.

Qualifications

• 10+ years of experience in ASIC design.
• Track record of successful tape outs in advanced process nodes.
• Strong knowledge of ASIC design methodologies.

Responsibilities

• Apply industry best practices in ASIC development.
• Design and code RTL modules written in Verilog/SystemVerilog.
• Simulate and perform hardware-based testing and verification.

Skills

Communication

Critical Thinking

Problem Solving

Agile Development

Education

B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science

Tools

Verilog/SystemVerilog

TCL/Python

C/C++

Job description

We are looking for aStaff ASIC Design Engineerto contribute to a team developing IP for both ASICs and FPGAs. The ideal candidate is a strong communicator, creative, a critical thinker, and able to analyze and resolve complex issues.

Responsibilities

• • Apply industry best practices in ASIC development to achieve best in class designs
  • Design, propose, and oversee the analysis/evaluation of hardware architectures
  • Design and code RTL modules written in Verilog/SystemVerilog
  • Simulate and perform hardware-based testing, debug, and verification
  • Scripting and basic software development in support of hardware design
  • Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment

Requirements

• • B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science
  • Track record of successful tape outs in advanced process nodes
  • 10+ years of experience in ASIC design
  • Experience in ASIC design methodologies, including code quality checking, synthesis, physical design, and power estimation design tools
  • Strong knowledge with RTL programming languages Verilog/SystemVerilog (preferred), or VHDL
  • Ability to read and write code in TCL/Python (C, C++ are assets)

Preferred Skills & Experience

• • Deep experience with ASIC or FPGA timing closure and physical design
  • Working experience with AMBA protocols, PCIe, UCIe, and HBM will be an asset
  • Experience with Agile development methodologies
  • Experience in technical leadership of small teams