Sr Staff Machine Learning ASIC Design Engineer

Qualcomm; Markham; On-site; CAD 90,000 - 150,000; Full time

Job summary

An established industry player is seeking a talented Sr Staff Machine Learning ASIC Design Engineer to join their innovative team in Markham. This role focuses on developing cutting-edge AI/ML hardware solutions, requiring a strong background in ASIC design and verification. Ideal candidates will have extensive experience with RTL design, micro-architecture, and collaboration across teams. You'll be part of a forward-thinking environment that values creativity and technical expertise, offering a chance to work on world-class projects that shape the future of wireless technology. If you're passionate about pushing the boundaries of technology, this opportunity is for you.

Qualifications

• 6+ years of ASIC-related experience in design and verification.
• Strong knowledge of ML HW development and bus protocols.

Responsibilities

• Develop micro-architecture and specifications based on design requirements.
• Design RTL that meets performance, area, and power targets.
• Collaborate with verification team on test plans and debugging.

Skills

Verilog

SystemVerilog

Analytical Skills

Debugging Skills

Communication Skills

Collaboration Abilities

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree

PhD

Tools

PERL

Python

TCL

Synthesis tools

Formal verification tools

Job description

Sr Staff Machine Learning ASIC Design Engineer

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Job Details

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Company:

Qualcomm Canada ULC

Job Area:

Engineering Group > ASIC Engineering

Summary:

QUALCOMM is a leading developer of next-generation wireless and multimedia technology. We seek an ASIC design engineer to develop world-class AI/ML HW IP solutions.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field + 6+ years of ASIC-related experience OR
• Master's degree + 5+ years OR
• PhD + 4+ years

Principal Duties:

• Develop micro-architecture and specifications based on high-level design requirements
• Design RTL that meets performance, area, and power targets
• Integrate pre-verified sub-IPs to build larger functionalities
• Conduct flow bring-up and report analysis (Linting, RTL Synthesis, CLP, CDC)
• Collaborate with verification team on test plans, debugging, and coverage analysis
• Develop SVA assertions for formal verification
• Communicate effectively across teams and manage multiple tasks efficiently

Preferred Qualifications:

• Experience with Verilog and SystemVerilog RTL
• Strong analytical, debugging, and detail-oriented skills
• Excellent communication and collaboration abilities
• Knowledge of clock domain crossing, ML HW development, FIFOs, bus verification, memory control, high-speed/low-power design, bus protocols (AHB, AXI)
• Experience with simulation, code coverage, design rule checks, scripting languages (PERL, Python, TCL, C), power analysis (UPF, CLP), synthesis tools, static timing analysis, formal verification tools

Additional Requirements:

• Legally permitted to work in Canada
• 5+ years of ASIC design/verification experience

Note:

Qualcomm is an equal opportunity employer. Accommodations are available for applicants with disabilities. Contact: [e-mail]