FPGA Designer: High Speed, Multi-Domain RTL

Fidus; Montreal; On-site; CAD 125,000 - 160,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

GRSP contributions

Profit-sharing bonus

Comprehensive benefits package

Job summary

Fidus in Canada seeks an experienced FPGA Designer to deliver complex FPGA-based systems. You will define architectures, implement RTL, integrate IP, run simulations, and support lab bring-up and debugging.

You’ll work with Xilinx and Intel devices, collaborate across teams, and participate in design reviews to ensure high-quality, timely solutions. A minimum of five years in RTL/Verilog/VHDL FPGA design and strong English communication are required.

Qualifications

• Minimum 5 years of RTL/Verilog/VHDL FPGA design experience.
• Experience with video systems, high-speed memory, and DSP or processor instantiations.
• Proven designs with Xilinx or Altera FPGA families and tool flows.
• Proficiency in Verilog, SystemVerilog, VHDL and simulators.
• RTL design and verification including test benches and timing analysis.
• Excellent English communication and customer interaction skills.

Responsibilities

• Develop complex FPGA/CPLD systems including architecture, IP, simulations and timing closure.
• Design FPGA-based systems using Xilinx and Intel devices and tools.
• Participate in design reviews to ensure quality and requirements alignment.
• Perform lab testing, debugging prototypes, and support hardware/software engineers.
• Prepare test plans, design descriptions, and user documentation.
• Provide technical input during pre-sales and project delivery.

Skills

RTL/Verilog/VHDL FPGA design

Video systems knowledge

Cross-functional collaboration

English communication

Education

B.A.Sc., B.Eng. or equivalent

Tools

Xilinx Vivado

Intel Quartus

ModelSim

Job description

Fidus in Canada seeks an experienced FPGA Designer to deliver complex FPGA-based systems. You will define architectures, implement RTL, integrate IP, run simulations, and support lab bring-up and debugging.

You’ll work with Xilinx and Intel devices, collaborate across teams, and participate in design reviews to ensure high-quality, timely solutions. A minimum of five years in RTL/Verilog/VHDL FPGA design and strong English communication are required.