Senior Package Layout Engineer

Semtech; Calgary; On-site; CAD 105,000 - 122,000; Full time

Job summary

Semtech Corporation seeks a motivated Package and PCB Layout Engineer to join the R&D hardware design team within the Signal Integrity Products unit. You will contribute high-speed layout expertise across multiple interconnect technologies and collaborate with cross-functional teams to deliver robust designs.

The role focuses on advancing 2D/2.5D/3D IC packaging, wafer-level interconnects, and tight design-rule compliance to support tape-outs and thermal/mechanical integration.

Qualifications

• Bachelor’s degree in engineering, physics, or related field.
• 5 years of layout experience in high-speed package/PCB.
• Strong knowledge of high-speed layout and design.
• Advanced knowledge of EDA layout tools (Cadence APD/Allegro).

Responsibilities

• Perform package design feasibility assessments with SI and thermo-mechanical teams.
• Develop multi-layer substrate and carrier layouts for 2D/2.5D/3D IC configurations.
• Develop wafer-level interconnect layouts using redistribution layers and wafer reconstruction technologies.

Skills

High-speed layout

EDA tools

PCB layout

Communication skills

Education

Bachelor’s degree in engineering, physics, or related field

Tools

Cadence APD

Allegro

Job description

Our Team

Semtech Corporation designs innovative semiconductor solutions and intellectual property cores for the world’s most advanced consumer connectivity and datacenter products. The Signal Integrity Products business unit’s R&D hardware design team is home to this role.

Our Team

Semtech Corporation designs innovative semiconductor solutions and intellectual property cores for the world’s most advanced consumer connectivity and datacenter products. The Signal Integrity Products business unit’s R&D hardware design team is home to this role.

Job Summary

We are looking for a motivated Package and PCB Layout Engineer to join our R&D hardware design team. The successful candidate will become a key member of the design engineering community of the Signal Integrity Products business unit, contributing innovative high-speed designs across a variety of interconnect technologies.

Responsibilities

• Depending on the candidate’s strengths and interests, responsibilities may include any of the following areas of focus:
• Perform package design feasibility assessments for the signal integrity experts, in conjunction with the manufacturing and thermo-mechanical engineering teams.
• Develop multi-layer substrate and carrier layouts to support 2D, 2.5D, and 3D IC configurations.
• Develop wafer-level interconnect layouts using wafer redistribution layers and wafer reconstruction technologies.

Minimum Qualifications

• Bachelor’s degree in engineering, physics, or another discipline relevant to the position.
• 5 years of layout experience in high-speed package and/or advanced PCB technologies.
• Solid knowledge of high-speed layout and electronic design.
• Advanced knowledge of EDA layout tools.
• Familiarity with PCB layout, as well as mechanical, thermal, and optical design.
• Understanding of RF, analog, and digital circuits.
• Ability to work in parallel with several cross-functional internal teams, while coordinating with local and international suppliers.
• Excellent written and oral communication skills, and the ability to work well with other team members.
• Ability to work independently with little supervision in a fast-paced environment.

Desired Qualifications

• Advanced knowledge of Cadence APD and Allegro.
• Knowledge of AI design acceleration features in EDA layout tools.
• Additional degrees or certificates in mechatronics, photonics, or electronics manufacturing.
• Familiarity with a variety of interconnect configurations, including chip-on-board, wirebond, flip-chip, optical assembly, and high-speed connectors.
• Familiarity with industry standards such as JEDEC and IPC.
• Experience troubleshooting PCBs and systems.
• High degree of creativity, determination, and innovation.

What Success Looks Like

• First 3 months: Become familiar with Semtech’s design flows, EDA tools, and supplier ecosystem, and complete [a first layout or feasibility assessment] under guidance.
• First 6 months: Independently own [number/type] package or PCB layouts from feasibility through release to fabrication, meeting schedule and design-rule requirements.
• First 12 months: Become a go-to contributor for [2.5D/3D IC, wafer-level, or another technology] and support [number] tape-outs or product releases.

Semtech is an equal opportunity employer and values the diversity, knowledge, and expertise of its workforce. Success, Ethics, Respect, and Alignment are the foundational values of our business and guide our relationships with employees, shareholders, customers, and other stakeholders.

The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.

All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.

We may leverage Artificial Intelligence (AI) tools to enhance efficiency during candidate screening, assessment, and recruitment. Final hiring decisions remain with our Hiring Teams, not AI systems.

A reasonable estimate of the pay range for this position is $105,000-$122,000 CAD. There are several factors taken into consideration in determining base salary, including but not limited to: job-related qualifications, skills, education and experience, as well as job location and the value of other elements of an employee’s total compensation package.