Senior FPGA Engineer - 4G/5G Radio DSP & RTL

Smartsearchonline; Ottawa; On-site; CAD 103,320,000 - 110,208,000; Full time

Job summary

Stefanini Group in Ottawa is seeking an FPGA Design Engineer with 4G/5G radio experience for an onsite, long-term contract in Kanata, Ontario, Canada. The role requires heavy Verilog/SystemVerilog RTL, DSP skills, and expertise with NR/LTE protocols.

You will design FPGA IP, implement RTL, verify with UVM, and collaborate with radio and software teams. Ideal candidates have 7+ years in FPGA design, experience with 4G/5G radios, and proficiency with Quartus, Vivado, MATLAB/Simulink.

Qualifications

• Proven FPGA design and RTL development experience.
• Expertise in NR/LTE/eCPRI/CPRI/PTP protocols and signal processing.
• Strong understanding of 4G/5G Radio architecture and O-RAN ecosystem.

Responsibilities

• Develop FPGA IP architecture for 4G/5G Radio Units.
• Implement complex RTL blocks (Verilog/SystemVerilog) and integrate into systems.
• Define verification plans using UVM and perform system-level validation.
• Collaborate with Radio Unit teams and software groups for HW-SW interoperability.

Skills

FPGA design

RTL development

4G/5G radio

Verilog/SystemVerilog

UVM verification

Git/GitHub

3GPP/O-RAN knowledge

Tools

Quartus

Vivado

MATLAB/Simulink

HDL Coder

Job description

Stefanini Group in Ottawa is seeking an FPGA Design Engineer with 4G/5G radio experience for an onsite, long-term contract in Kanata, Ontario, Canada. The role requires heavy Verilog/SystemVerilog RTL, DSP skills, and expertise with NR/LTE protocols.

You will design FPGA IP, implement RTL, verify with UVM, and collaborate with radio and software teams. Ideal candidates have 7+ years in FPGA design, experience with 4G/5G radios, and proficiency with Quartus, Vivado, MATLAB/Simulink.