FPGA Design Engineer

Smartsearchonline; Ottawa; On-site; CAD 103,320,000 - 110,208,000; Full time

Job summary

Stefanini Group in Ottawa is seeking an FPGA Design Engineer with 4G/5G radio experience for an onsite, long-term contract in Kanata, Ontario, Canada. The role requires heavy Verilog/SystemVerilog RTL, DSP skills, and expertise with NR/LTE protocols.

You will design FPGA IP, implement RTL, verify with UVM, and collaborate with radio and software teams. Ideal candidates have 7+ years in FPGA design, experience with 4G/5G radios, and proficiency with Quartus, Vivado, MATLAB/Simulink.

Qualifications

• Proven FPGA design and RTL development experience.
• Expertise in NR/LTE/eCPRI/CPRI/PTP protocols and signal processing.
• Strong understanding of 4G/5G Radio architecture and O-RAN ecosystem.

Responsibilities

• Develop FPGA IP architecture for 4G/5G Radio Units.
• Implement complex RTL blocks (Verilog/SystemVerilog) and integrate into systems.
• Define verification plans using UVM and perform system-level validation.
• Collaborate with Radio Unit teams and software groups for HW-SW interoperability.

Skills

FPGA design

RTL development

4G/5G radio

Verilog/SystemVerilog

UVM verification

Git/GitHub

3GPP/O-RAN knowledge

Tools

Quartus

Vivado

MATLAB/Simulink

HDL Coder

Job description

Job Details

FPGA Design Engineer KANATA,On Posted:9/30/2026 Job Description Job ID#: 65070

Job Category: Information Technology

Position Type: Contract

Duration: Long Term

Remaining Positions: 1

Details: Stefanini Group is hiring! Stefanini is looking for FPGA Design Engineer with Radio experience (Onsite Role) in Ottawa, Ontario, Canada

22 Total Days PTO (See Below the breakdown)

• * 10 Days Time-off (80 Hours of Time-Off- Accrual Basis)
• * 9 Holidays on average throughout the year
• * 3 Personal Days

IMP: Digital Signal Processing (DSP) is a must have skill for the role.

Ideal Candidate: FPGA designer engineer with Radio experience. Working with 4G/5G Radios. 7+ years of experience Heavy System Verilog and RTL experience.

They DO NOT USE VHDL.

Tools: Altera Quartus. Matlab/Simulink for modeling Axi and Ethernet protocol experience are more important than other high-speed experience.

Responsibilities

• Works on unusually complex problems and provides highly innovative solutions Uses independent judgment to accomplish goals and objectives
• Has insight into industry trends and communicates vision to guide organizational strategy and long-range planning
• Lends research and contributes to evaluations, project plans and budgets for new products or updates existing products
• Acts as consultant on critical projects that impact long term organizational goals and objectives
• Leads teams, gives technical guidance and communicates with senior management on progress Identifies or creates solutions that are likely to contribute to the development of new company concepts
• Expected to set standards and achieve cost targets for product cost through proper design choices, component selection or supplier selection
• Demonstrated expertise in competitive analysis
• May actively seek customer input and take responsibility for internal and external customer situations
• Determines requirements and functional specifications for entire system, under only consultative direction.

Job Requirements Details

What You'll Do

Design & Architecture

• Develop FPGA IP architecture for 4G/5G Radio Units.
• Contribute to system-level design aligned with 3GPP and O-RAN Alliance specifications.

Implementation

• Implement complex RTL blocks (Verilog/SystemVerilog) and integrate into larger systems.
• Optimize FPGA resource utilization and ensure timing closure.

Validation & Testing

• Define and execute verification plans using UVM and advanced techniques.
• Perform simulation and system-level FPGA validation.

Collaboration

• Work closely with Radio Unit development teams for seamless integration.
• Partner with software teams to ensure hardware-software interoperability.
• Mentor junior engineers and participate in technical reviews.

What You'll Bring

Essential Requirements

• Proven experience in FPGA design and RTL development.
• Expertise in NR/LTE/eCPRI/CPRI/PTP protocols and signal processing. This is a specialized subset of Digital Signal Processing (DSP) specifically focused on telecommunications and wireless fronthaul/baseband engineering.
• Familiarity with JESD204B/C, Ethernet, PCIe, AXI, and high-speed SERDES.
• Tools: Quartus, Vivado, MATLAB/Simulink, HDL Coder.
• Knowledge of UVM and verification methodologies.
• Strong understanding of 4G/5G Radio architecture and O-RAN ecosystem.
• Experience with Git/GitHub and version control workflows.

Desirable Skills

• 7+ years of FPGA design experience in wireless or high-speed systems.
• Experience in high-volume wireless products and IP development.
• Contributions to standards bodies or technical forums (O-RAN, 3GPP).

Stefanini takes pride in hiring top talent and developing relationships with our future employees. Our talent acquisition teams will never make an offer of employment without having a phone conversation with you. Those face-to-face conversations will involve a description of the job for which you have applied. We also speak with you about the process including interviews and job offers.

About Stefanini Group

The Stefanini Group is a global provider of offshore, onshore and near shore outsourcing, IT digital consulting, systems integration, application, and strategic staffing services to Fortune 1000 enterprises around the world. Our presence is in countries like the Americas, Europe, Africa, and Asia, and more than four hundred clients across a broad spectrum of markets, including financial services, manufacturing, telecommunications, chemical services, technology, public sector, and utilities. Stefanini is a CMM level 5, IT consulting company with a global presence. We are CMM Level 5 company

Pay Range: $ 75.00 - $ 80.00