Senior CPU Clock Architect — High-Perf, Low-Power

NUVACORE; Markham; On-site; CAD 199,000 - 356,000; Full time

Job summary

Nuvacore is building a ground-up high-performance, low-power CPU for next-generation compute workloads. As a Custom Clock Design and Distribution (CCD) Engineer, you will architect and deliver the clock generation and distribution networks that set frequency, skew, jitter, and power for the product.

You will drive end-to-end clock-network closure, signoffs, and collaborate across PLL, CAD, physical design, and DFT teams to ensure silicon-ready clock IP for high-volume products.

Qualifications

• BS or MS degree in EE with relevant clock-design experience.
• Hands-on transistor-level clock design and CTS experience.
• Experience with high-frequency clock networks and PPA targets.
• Strong SPICE, device physics, RC delay and signal integrity knowledge.
• STA signoff across Functional and DFT modes.
• Track record delivering clock networks through tape-out with silicon-validated PPA.

Responsibilities

• Architect and drive end-to-end clock generation and distribution methodology.
• Design and characterize clock circuits at transistor level across PVT corners.
• Own clock-network closure: skew, latency, jitter analysis and signoff.
• Collaborate with PLL/FLL, timing, power, CAD, physical design, and DFT teams.

Skills

Clock design

Clock distribution

CMOS nodes

SPICE analysis

STA signoff

PPA targets

Tape-out experience

Communication

Scripting

DFT integration

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

H-tree CTS

Clock-tree synthesis

SPICE

DFT tooling

Job description

Nuvacore is building a ground-up high-performance, low-power CPU for next-generation compute workloads. As a Custom Clock Design and Distribution (CCD) Engineer, you will architect and deliver the clock generation and distribution networks that set frequency, skew, jitter, and power for the product.

You will drive end-to-end clock-network closure, signoffs, and collaborate across PLL, CAD, physical design, and DFT teams to ensure silicon-ready clock IP for high-volume products.