Lead SoC Architect - AI Data-Center Fabric & Memory

NUVACORE; Canada; On-site; CAD 190,000 - 240,000; Full time

Job summary

NUVACORE is building a general-purpose CPU core for AI-era, data-center-scale workloads. We seek a Lead SoC Architect to own the SoC architecture—fabric, memory, I/O, power, and security—and to set direction across design, verification, physical design, and software.

You will drive architectural trade-offs, review RTL and verification plans, and mentor engineers while partnering with packaging and software teams to deliver a scalable, secure, multi-die capable platform.

Qualifications

• 20+ years in SoC or system architecture, from definition through tape-out and production.
• Deep expertise in coherent/non-coherent interconnect and fabric architecture and coherency protocols.
• Strong grounding in cache hierarchies and memory controller design (DDR5/DDR6, LPDDR5/LPDDR6).
• Working knowledge of PCIe/CXL I/O architecture and System MMU/IO virtualization.
• Die-to-die interconnect and chiplet-based partitioning experience.
• Experience integrating in-house and third-party IP with vendors and internal teams.

Responsibilities

• Own the overall SoC architecture: fabric topology, memory subsystem, I/O, power management, and security.
• Define architectural direction, perform system-level trade-offs, and drive reviews with design, verification, and software.
• Architect the coherent fabric, home nodes, cache hierarchy, and coherency protocol choices.
• Lead die-to-die interconnect, chiplet partitioning, and integration of IP across the SoC.
• Collaborate with physical design, packaging teams, and software to optimize floorplanning and power/thermal decisions.
• Mentor engineers and represent SoC architecture in cross-functional forums.

Job description

NUVACORE is building a general-purpose CPU core for AI-era, data-center-scale workloads. We seek a Lead SoC Architect to own the SoC architecture—fabric, memory, I/O, power, and security—and to set direction across design, verification, physical design, and software.

You will drive architectural trade-offs, review RTL and verification plans, and mentor engineers while partnering with packaging and software teams to deliver a scalable, secure, multi-die capable platform.