CPU Clock Distribution and Custom Clock Design

NUVACORE; Markham; On-site; CAD 199,000 - 356,000; Full time

Job summary

Nuvacore is building a ground-up high-performance, low-power CPU for next-generation compute workloads. As a Custom Clock Design and Distribution (CCD) Engineer, you will architect and deliver the clock generation and distribution networks that set frequency, skew, jitter, and power for the product.

You will drive end-to-end clock-network closure, signoffs, and collaborate across PLL, CAD, physical design, and DFT teams to ensure silicon-ready clock IP for high-volume products.

Qualifications

• BS or MS degree in EE with relevant clock-design experience.
• Hands-on transistor-level clock design and CTS experience.
• Experience with high-frequency clock networks and PPA targets.
• Strong SPICE, device physics, RC delay and signal integrity knowledge.
• STA signoff across Functional and DFT modes.
• Track record delivering clock networks through tape-out with silicon-validated PPA.

Responsibilities

• Architect and drive end-to-end clock generation and distribution methodology.
• Design and characterize clock circuits at transistor level across PVT corners.
• Own clock-network closure: skew, latency, jitter analysis and signoff.
• Collaborate with PLL/FLL, timing, power, CAD, physical design, and DFT teams.

Skills

Clock design

Clock distribution

CMOS nodes

SPICE analysis

STA signoff

PPA targets

Tape-out experience

Communication

Scripting

DFT integration

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

H-tree CTS

Clock-tree synthesis

SPICE

DFT tooling

Job description

Full-time ** · US / Canada / India**

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of the CPU clock design team, you will architect and deliver the clock generation and distribution networks that set the frequency, skew, jitter, and power ceiling for the product.

THE ROLE

As a Custom Clock Design and Distribution (CCD) Engineer, you will participate in the following :

• Architect and drive the end-to-end clock generation and distribution methodology using H-tree, mesh, spine, and multi-source clock-tree synthesis for high-frequency CPU cores, co-optimizing skew, insertion delay, jitter, duty-cycle distortion, and clock power.

• Design and characterize custom clock circuits at transistor level clock buffers and repeaters, dividers, deskew and duty-cycle correction, clock-gating and clock-mux cells meeting PPA targets across PVT corners.

• Own end-to-end clock-network closure: SPICE-driven skew, latency, and jitter analysis, EM/IR and signal-integrity signoff on the clock grid, and STA correlation (OCV/AOCV/POCV) across Functional and DFT modes.

• Partner with PLL/FLL, timing, power, CAD, physical design, and DFT teams aligning clock source models, jitter budgets, and power-aware clocking and drive Tools, Flows, and Methodology (TFM), including clock-analysis automation and team-wide best practices.

MINIMUM QUALIFICATIONS

• Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in clock design, clock distribution, and/or custom circuit design.

• Hands-on transistor-level design experience with clock dividers, deskew and duty-cycle correction, clock-gating and mux cells at advanced CMOS nodes.

• Proven experience constructing and analyzing low-skew, low-power clock distribution networks using H-tree, mesh, spine, and multi-source CTS for high-frequency CPUs.

• Strong SPICE simulation and analysis skills, with solid grounding in device physics, RC delay, and signal integrity applied to clock-path design and verification.

• Well-versed in STA and clock timing signoff including setup, hold, duty cycle closure across Functional and DFT (Design for Test) modes.

• Demonstrated track record delivering clock networks and/or clocking IP through tape-out, with silicon-validated PPA — frequency, skew, jitter, and power — in high-volume products.

• Strong communication and collaboration skills, comfortable working directly with PLL, CAD, physical design, and foundry partner teams.

REQUIREMENTS — PREFERRED

• Proficiency with PLL/FLL specifications, clock source modeling, skew estimation, jitter budgeting, and jitter/duty-cycle measurement.

• Experience with power-aware clocking — clock gating, DVFS, clock-skipping, and resonant or mesh-based clocking strategies for clock-power reduction.

• Deep understanding of clock-network signoff — EM/IR on the clock grid, dynamic voltage-drop-aware timing, crosstalk and noise, and Monte Carlo variation studies.

• Experience with testchip clock development and benchmarking, and partnering directly with foundries on PDK bring-up and clock-device co-optimization (DTCO) at leading-edge nodes.

• Familiarity with the full clock flow — architecture, circuit design, physical implementation of the clock network, and timing/model generation — at block and full-chip level.

• Proficient in Python, Perl, or TCL to build and improve clock analysis, characterization, and methodology automation.

• Experience using Agentic AI tools for productivity and automation.

$140,000 - $250,000 a year