Senior ASIC (Front End) Design Engineer

Ethernovia, Inc.; Toronto; Vor Ort; CAD 140.000 - 190.000; Vollzeit

Benefits dieser Stelle

Pre IPO stock options

Flexible hours

Medical, dental and vision insurance

Zusammenfassung

Ethernovia, Inc. invites applications for a Senior ASIC Front End Design Engineer in Toronto.

You will drive all aspects of digital SoC design, from micro-architecture to timing, interfacing with system architects, software, hardware and verification teams to deliver advanced automotive semiconductors. You will help define high-performance custom silicon, supporting multiple protocols and data processing across disciplines.

Qualifikationen

• 10+ years of ASIC RTL design and/or architecture experience.
• Proven track record in development of complex SoCs.
• Strong understanding of digital design fundamentals and methodologies.
• Proficiency in Verilog/SystemVerilog and simulation tools.
• Self-motivated with ability to work independently and in a team.

Aufgaben

• Responsible for all aspects of digital SoC design from micro-architecture specification through RTL, verification, synthesis, lint, CDC, LEC and STA to meet target PPA.
• Collaborate with system architects, software, hardware and verification engineers to design and deliver advanced automotive communication semiconductors and systems.
• Develop and define a high-performance, custom silicon with diverse protocols, algorithms and applications.
• Specify ASIC internal and external interactions, data flow and processing algorithms across multiple disciplines.

Kenntnisse

ASIC RTL design

Digital design fundamentals

SystemVerilog

Self-motivated

Team collaboration

Ausbildung

BS in Electrical Engineering or Computer Science

MS in Electrical Engineering or Computer Science

Tools

Verilog

SystemVerilog

Make

Perl

TCL

C/C++

Jobbeschreibung

Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications.

Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds’ leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date:

• (financial backers include: Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital)

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.

With talented employees on 4 continents, we have filed 50+ patents to date.

Join Ethernovia’s team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting edge designs from concept to silicon to the future of mobility.

Summary:

• As a Senior ASIC(Front End) Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.
• Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems.
• You will be on the leading edge of the development and definition of advanced, high-performance custom silicon that embodies functions from a wide range of protocols, algorithms, and applications.
• Expected to flesh out product definitions with precise specifications of: an ASIC's internal and external interactions, data flow, processing algorithms across a number of disciplines, resource management, and software interfaces.
• You will be a trusted self-starter who can work with very little guidance or oversight.
• This position is located in: Toronto, Canada - Hybrid

Key Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC RTL design and/or architecture experience
• Proven track record with the development of complex SoCs
• Strong understanding of digital design fundamentals and methodologies
• In-depth knowledge of Verilog/System Verilog and simulation tools.
• Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:

Experience in any of the following areas:

• Networking (Ethernet MAC, PHY/PCS, Switching, TCP/IP, PCIe and other industry standard protocols)
• Digital signal processing filters
• Digital Mixed-Signal modeling, design, and integration
• Video standards, protocols, processing
• Perl, TCL, C/C++, Make

Personal Skills:

• Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Flexible hours
• Medical, dental and vision insurance for employees

#LI-Hybrid