Principal Design Verification Engineer

Synopsys, Inc.; Ottawa; On-site; CAD 90,000 - 150,000; Full time

Job summary

Join a forward-thinking company as a Principal Design Verification Engineer, where your expertise in ASIC verification and proficiency in Verilog and System Verilog will drive innovation. You'll develop test benches, collaborate with architects, and lead verification processes from specification to tape out. This role is crucial in ensuring the robustness of high-performance silicon chips, contributing to groundbreaking technologies like AI and self-driving cars. If you're a detail-oriented problem solver who thrives in dynamic environments, this opportunity promises to be both challenging and rewarding, fostering your career in a collaborative team dedicated to excellence.

Benefits

Health and wellness benefits

Financial benefits

Comprehensive rewards package

Qualifications

• 12+ years of experience in ASIC verification at SOC/block levels.
• Strong skills in Verilog, System Verilog, and scripting languages.

Responsibilities

• Develop and verify integrated IP subsystems for global customers.
• Optimize verification processes for efficiency and effectiveness.

Skills

Verilog

System Verilog

Perl

Python

UVM verification

Debugging

ASIC Verification

Education

BSEE in Electrical Engineering

MSEE in Electrical Engineering

Tools

Makefile

Industry tools

Job description

Principal Design Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

A highly skilled and experienced ASIC Design Verification Engineer who thrives in a dynamic and innovative environment. With a strong background in ASIC verification at both the SOC and block levels, you possess exceptional skills in Verilog, System Verilog, and scripting languages like Perl/Python. Your proficiency in UVM verification environments and industry tools allows you to optimize verification processes efficiently. You have a knack for debugging and can independently root cause issues, providing technical leadership from initial specification to tape out. Your excellent communication and problem-solving skills enable you to work seamlessly with architects and RTL designers. Experience in DDR PHY and memory subsystems is a plus.

What You’ll Be Doing:

• Developing test benches and verifying integrated IP Subsystems for global customers.
• Triage issues by working independently with architects and RTL designers.
• Providing technical leadership on verification from initial specification to tape out.
• Optimizing verification processes for efficiency and effectiveness.
• Debugging and root causing issues to ensure high-quality deliverables.
• Collaborating with cross-functional teams to meet project goals and deadlines.

The Impact You Will Have:

• Ensure the robustness and reliability of our high-performance silicon chips.
• Contribute to the development of next-generation processes and models for chip manufacturing.
• Help customers optimize chips for power, cost, and performance.
• Reduce project schedules significantly through efficient verification processes.
• Drive technological innovation in the Era of Smart Everything, including AI and IoT.
• Support the creation of groundbreaking technologies like self-driving cars and 5G.

What You’ll Need:

• BSEE in EE with 12+ years of relevant experience or MSEE with 10+ years of relevant experience.
• Experience in ASIC Verification at the SOC level and block level.
• Exceptional Verilog, System Verilog, Perl/Python scripting, Makefile skills.
• Proficiency in UVM verification environment.
• Experience with industry tools and ability to optimize processes for verification.
• Solid debugging skills and ability to root cause issues.
• Verification experience in DDR PHY, memory subsystem is a plus.

Who You Are:

• Excellent communicator with strong problem-solving skills.
• Independent worker who can take initiative and lead projects.
• Detail-oriented and highly organized.
• Collaborative team player with a passion for innovation.
• Adaptable and able to thrive in a fast-paced environment.

The Team You’ll Be A Part Of:

You will join our dedicated DDR PHY IP team, a group of experts focused on delivering high-quality integrated IP subsystems. Our team works collaboratively across various functions to ensure the successful design and verification of advanced silicon chips. We are committed to driving innovation and excellence in all our projects.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.