Principal ASIC Verification Engineer

Nokia; Ottawa; On-site; CAD 120,000 - 160,000; Full time

Job summary

A leading telecommunications company is seeking an ASIC Verification Engineer to contribute to the development of verification infrastructure and execute testing for digital ASICs. Candidates should have a Master's degree and over 10 years of experience in the ASIC verification field, with strong skills in System Verilog and Python.

Qualifications

• 10+ years of relevant experience in ASIC verification.
• Fluency in System Verilog, scripting languages like Python.
• Intimate knowledge of UVM methodology and verification tools.

Responsibilities

• Contribute to verification infrastructure development.
• Develop System Verilog/UVM-based test plans and traffic generators.
• Lead team or work independently to deliver tasks.

Skills

System Verilog

Python

Problem-solving

Communication

Education

Master's degree

Bachelor's degree in CS/EE

Tools

UVM methodology

Formal verification tools

Job description

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running.The Network Infrastructuregroup is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.

Qualifications

• Master's degree desired, Bachelor's degree in CS/EE is required.
• Minimum 10+ years of relevant experience in the ASIC verification field.
• Should have worked on developing/implementing test plans at the block or sub-chip levels for complex ASICs.
• Fluent in System Verilog and scripting languages such as Python.
• Must have intimate knowledge of UVM methodology.
• Knowledgeable about assertions and functional coverage.
• Experience with code coverage and formal verification tools; familiarity with evolving verification methodologies.
• Strong problem-solving skills.
• Very good communication skills, ability, and desire to work in a geographically diverse team environment.
• Will be responsible for the definition, development, and execution of self-checking tests for complex digital ASICs.
• Knowledge of DSP and/or FEC will be desirable.

Responsibilities

• Contribute significantly to verification infrastructure development.
• Development of System Verilog/UVM-based protocol/traffic generators/checkers, development of a test plan based on functional requirements, and applicable standards requirements.
• Work as an independent contributor or lead a team to deliver defined tasks.