Principal AI Infrastructure Applications Engineer

Astera Labs; Vancouver; On-site; CAD 165,000 - 210,000; Full time

Job summary

Astera Labs is redefining AI infrastructure with Scorpio smart fabric switches, guiding hyperscalers and system builders from evaluation to production deployment. You will lead customer engagements, bring-up, and debug of Scorpio platforms, translating requirements to actions for product, silicon, and firmware teams.

The role centers on driving cross-functional initiatives, authoring collateral, and shaping features across PCIe Gen 6/7 and UALink platforms, influencing the roadmap of a

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 8+ years experience in product applications, systems engineering, or post-silicon validation on high-speed connectivity or networking silicon.
• Strong understanding of PCIe, Ethernet, UALink, UCIe, or similar interfaces.
• Hands-on bring-up, debug, and system-level integration using scopes and protocol analyzers.
• Experience engaging with hyperscalers, cloud, or OEM/ODM customers on complex deployments.
• Excellent communication skills suitable for customer-facing work.

Responsibilities

• Lead technical engagements with hyperscalers, ODMs, and AI system partners from architecture discussions through design-in and evaluation
• Own on-site and remote bring-up, debug, and performance tuning of Scorpio-based platforms at customer sites
• Translate customer requirements into actionable feedback for product, silicon, and firmware teams

Skills

8+ years experience

High-speed interfaces

Customer facing

Leadership

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

Protocol analyzers

Job description

Astera Labs is redefining AI infrastructure with Scorpio smart fabric switches, guiding hyperscalers and system builders from evaluation to production deployment. You will lead customer engagements, bring-up, and debug of Scorpio platforms, translating requirements to actions for product, silicon, and firmware teams.

The role centers on driving cross-functional initiatives, authoring collateral, and shaping features across PCIe Gen 6/7 and UALink platforms, influencing the roadmap of a