Principal Product Applications Engineer - Scorpio

Astera Labs; Vancouver; On-site; CAD 165,000 - 210,000; Full time

Job summary

Astera Labs seeks a Principal Product Applications Engineer for the Scorpio team to be the technical face of our switching portfolio, guiding hyperscalers from evaluation to deployment. You will lead customer system design-in and Scorpio-related debugging, develop collateral, and drive features across PCIe Gen 6/7 & UALink.

You will mentor engineers, author technical materials, and partner with cross-functional teams to deliver production-ready solutions at a fast-growing semiconductor company

Qualifications

• Bachelor's degree in a related field is required or equivalent.
• 8+ years in product applications, systems engineering, or post-silicon validation.
• Experience with hyperscaler or OEM/ODM customer engagements is a plus.
• Strong communication to translate complex tech to customers.

Responsibilities

• Lead customer engagements from architecture discussions to design-in.
• Own on-site and remote bring-up, debug, and performance tuning.
• Translate customer requirements into feedback for product teams.
• Influence post-silicon validation plans and system integration.
• Debug multi-domain issues across protocols, SI/PI, firmware, and software.
• Collaborate with hardware, firmware, and SI/PI teams to deliver solutions.
• Serve as Scorpio applications expert across internal teams and customers.
• Mentor junior engineers and contribute to white papers and collateral.

Skills

8+ years experience

High-speed interfaces

Customer engagements

Technical leadership

Education

Bachelor's degree in Electrical/Computer Eng

Tools

Scopes & BERTs

Protocol analyzers

Lab equipment

PCIe/UCIe tools

Job description

Astera Labs is redefining the fabric of AI infrastructure with our Scorpio Smart Fabric Switches — purpose-built silicon that connects GPUs, CPUs, and accelerators at rack scale. As a Principal Product Applications Engineer on the Scorpio team, you will be the technical face of our switching portfolio to the world's leading hyperscalers, AI system builders, and platform partners, guiding them from first evaluation through production deployment.

This is a high-impact, customer-facing role at the center of one of the fastest-growing categories in semiconductors. You will lead customer system design-in and Scorpio-related debug, develop customer-facing collateral, lead cross-functional Scorpio-related initiatives, and drive and validate new features across PCIe Gen 6 / Gen 7 & UALink platforms — directly influencing the roadmap of a hyper-growth company powering the next generation of AI compute.

Key Responsibilities

• Customer Enablement
• Lead technical engagements with hyperscalers, ODMs, and AI system partners from architecture discussions through design-in and evaluation
• Own on-site and remote bring-up, debug, and performance tuning of Scorpio-based platforms at customer sites
• Translate customer requirements into actionable feedback for product, silicon, and firmware teams
• Influence post-silicon validation plans and execute system-level integration on next-generation switching platforms
• Debug complex multi-domain issues spanning protocol (UALink, UCIe, PCIe Gen 6/7), signal integrity, firmware, and software stacks
• Partner with hardware, firmware, and SI/PI teams to root-cause issues and deliver production-ready solutions
• Technical Leadership & Cross-Functional Influence
• Serve as the go-to Scorpio applications expert across sales, marketing, product, and engineering
• Mentor junior applications engineers and represent Astera Labs at industry forums, standards bodies, and customer executive reviews
• Author white papers, technical collateral, and training materials that scale the team's impact

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• 8+ years of experience in product applications, systems engineering, or post-silicon validation on high-speed connectivity or networking silicon
• Strong understanding of the physical layer and high-speed serial interfaces (PCIe, Ethernet, UALink, UCIe, or similar)
• Hands-on experience with lab bring-up, debug, and system-level integration — including scopes, BERTs, and protocol analyzers
• Proven track record engaging directly with hyperscaler, cloud, or Tier-1 OEM/ODM customers on complex technical deployments
• Excellent communication skills with the ability to translate deep technical detail into clear customer-facing narratives

Preferred Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, or a related field
• Direct experience with PCIe Gen 6 / Gen 7, UALink, or UCIe protocols and compliance testing
• Familiarity with AI/ML rack-scale architectures, GPU fabrics, and accelerator interconnects
• Scripting and automation experience (Python, shell) for validation and diagnostics
• Background contributing to standards bodies (PCI-SIG, UALink Consortium, UCIe) or authoring technical publications

Salary range is $165,000 to $210,000 CAN depending on experience, level, and business need. This role may be eligible for discretionary bonuses, incentives, and benefits.