Layout Design Intern (Fall 2026)

Ciena; Ottawa; On-site; CAD 34,000 - 48,000; Full time

Job summary

Ciena is offering a 4-month student internship in Ottawa focused on high-speed analog/mixed-signal layout for WaveLogic technology. You will work with senior designers to develop custom layouts, perform rigorous verification (DRC/LVS/EM/IR drop), and improve layout efficiency within a collaborative engineering team.

Ideal candidates are actively enrolled in Electrical Engineering, have hands-on CMOS layout experience, and can read and debug DRC/LVS reports.

Qualifications

• Actively enrolled in Electrical Engineering or related degree.
• Hands-on analog/mixed-signal layout in deep sub‑micron CMOS.
• Strong layout techniques: floorplanning, device matching, parasitic minimization, shielding, EM, IR drop.
• Experience creating layouts for analog or mixed‑signal blocks such as op-amps or current mirrors.
• Familiar with semiconductor manufacturing processes and foundry rules.
• Experience using Cadence Virtuoso and Calibre.
• Ability to interpret and debug DRC/LVS reports.

Responsibilities

• Contribute to layout feasibility studies with senior analog designers.
• Develop custom layouts for analog and mixed‑signal blocks.
• Perform DRC/LVS/EM/IR drop analyses to ensure layout quality.
• Explore new layout tool features to improve productivity.
• Collaborate with circuit designers to identify and resolve layout risks early in the design cycle.
• Provide clear status updates in team meetings and knowledge-sharing sessions.

Skills

Layout design

CMOS tech

Cadence Virtuoso

Calibre LVS/DRC

Floorplanning

Parasitic minimization

IR drop analysis

Device matching

Education

Electrical Engineering degree program

Tools

Cadence Virtuoso

Siemens Calibre

Job description

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.

The Opportunity:

Work term of 4 months starting in Spetember/October 2026.

The WaveLogic™ family of products is a cornerstone of Ciena’s optical fiber transmission solutions and a key contributor to the company’s leadership in the global telecommunications industry. This opportunity provides hands‑on exposure to advanced high-speed analog and mixed‑signal circuit design within a team that has contributed to more than three decades of innovation in broadband fiber‑optic modems. The role offers the opportunity to contribute to next‑generation high‑speed circuit development in a collaborative engineering environment.

How you will make an impact:

• Contribute to layout feasibility studies in partnership with senior analog designers, evaluating design trade-offs and layout strategies for high-speed circuits
• Develop custom layouts for advanced analog and mixed‑signal blocks, following structured methodologies for floorplanning, placement, and routing
• Execute comprehensive physical verification, including design rule checks (DRC), layout versus schematic (LVS), electromigration (EM), and infrared (IR) drop analysis to ensure layout quality and reliability
• Explore new layout tool features, flows, and processes to enhance efficiency and productivity
• Collaborate closely with circuit designers and layout engineers to identify and resolve layout‑related risks early in the design cycle
• Provide clear status updates and participate in team meetings, design discussions, and knowledge‑sharing activities

The must haves:

• Education: Actively enrolled in a degree program in Electrical Engineering or a related field,
• Hands‑on experience with custom analog and mixed‑signal layout design in deep sub‑micron complementary metal‑oxide semiconductor (CMOS) technologies
• Strong understanding of layout techniques, including floorplanning, device matching, parasitic minimization, shielding, electromigration, and IR drop considerations
• Experience creating custom layouts for analog or mixed‑signal blocks such as operational amplifiers or current mirrors
• Familiarity with semiconductor manufacturing processes and foundry design rules
• Experience using industry-standard layout tools such as Cadence Virtuoso and Siemens Calibre
• Ability to interpret and debug DRC and LVS reports effectively

Nice to haves:

• Exposure to high-speed data converter or phase‑locked loop (PLL) layout design
• Familiarity with bipolar CMOS (BiCMOS) technologies
• Scripting experience using PERL or SKILL to support layout automation or productivity improvements
• Experience collaborating in cross‑functional hardware design teams
• Strong analytical skills with the ability to proactively identify layout‑sensitive circuit structures

Pay Range:

The hourly pay rate for this position is $25.50 – $35.00

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company‑paid holidays, paid sick leave, and vacation pay as required by applicable laws.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is anEqual Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.