FPGA Placement & Compiler Tools Engineer

207 Altera Semiconductor Technology Canada ULC; Toronto; On-site; CAD 110,000 - 120,000; Full time

Job summary

Altera is seeking a skilled engineer in Toronto to develop and optimize FPGA placement algorithms within the compiler toolchain. The role focuses on timing-driven placement, QoR improvements, and seamless integration with the FPGA flow to deliver high-performance designs.

Ideal candidates hold a Bachelor's in CS or ECE, strong C++ skills, and experience with Verilog, Python, and TCL. This on-site, full-time position offers a Canadian salary range and exposure to large, customer-focused FPGA

Qualifications

• Bachelor's degree in CS, Computer Engineering, or related field.
• Working experience with C++.
• Experience with Verilog, Python and TCL is a plus.

Responsibilities

• Placement Algorithm Development: Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
• Compiler Flow Enhancement: Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams.
• Performance Optimization: Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.
• Timing-Driven Placement: Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs.
• Debug & Analysis: Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.
• Toolchain Integration: Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.

Skills

C++

Verilog

Python

TCL

Education

Bachelor's Degree in CS, Computer Engineering, or related field

Tools

Verilog

Python

TCL

Job description

Altera is seeking a skilled engineer in Toronto to develop and optimize FPGA placement algorithms within the compiler toolchain. The role focuses on timing-driven placement, QoR improvements, and seamless integration with the FPGA flow to deliver high-performance designs.

Ideal candidates hold a Bachelor's in CS or ECE, strong C++ skills, and experience with Verilog, Python, and TCL. This on-site, full-time position offers a Canadian salary range and exposure to large, customer-focused FPGA