FPGA Development Tools Engineer - Placer

Altera; Toronto; On-site; CAD 110,000 - 120,000; Full time

Job summary

Altera, a leader in FPGA innovation, is seeking a software engineer to design and optimize FPGA placement algorithms within the compiler toolchain, based in Toronto, Canada.

You will improve timing, QoR, and resource utilization, collaborate with routing, synthesis, and timing teams, and contribute to end-to-end compilation flows. Candidates should have a CS/CE degree and hands-on C++, Verilog, Python, and TCL experience. This role offers a competitive CAD salary with performance incentives.

Qualifications

• Bachelor's degree in CS/CE or related field.
• Working experience with C++.
• Experience with Verilog, Python and TCL is a plus.

Responsibilities

• Placement Algorithm Development: Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
• Compiler Flow Enhancement: Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams.
• Performance Optimization: Improve runtime performance, scalability, and QoR for large and complex customer designs.
• Timing-Driven Placement: Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs.
• Debug & Analysis: Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.
• Toolchain Integration: Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.

Skills

C++

Verilog

Python

TCL

Education

Bachelor's Degree in CS, Computer Engineering, or related field

Job description

Job Details

Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are at the core of enabling customers to efficiently map complex designs to cutting-edge FPGA architectures. This role focuses on developing and optimizing FPGA placement algorithms within the compiler toolchain, directly impacting performance, power efficiency, and overall design quality.

Key Responsibilities

• Placement Algorithm Development: Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
• Compiler Flow Enhancement: Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams.
• Performance Optimization: Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.
• Timing-Driven Placement: Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs.
• Debug & Analysis: Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.
• Toolchain Integration: Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.

Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position's location, as well as the candidate’s experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success. Estimated Salary Range: $110K- $120K CAD

Canadian work experience is not required for this role.

Applicants must be eligible for any required Canada export authorizations.

Qualifications

• Bachelor's Degree in CS, Computer Engineering, or related field
• Working experience with C++
• Experience with Verilog, Python and TCL is a plus

Job Type: Regular Shift: Shift 1 (Canada). Primary Location: Toronto, Ontario, Canada. Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About Altera

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities.

Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.