Senior FPGA Compiler & Placement Engineer

altera; Toronto; On-site; CAD 129,000 - 187,000; Full time

Benefits offered by this job

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Job summary

Altera in Toronto, Ontario, is seeking an FPGA Compiler Engineer (Placer) to join our Compiler team. You will design and optimize placement algorithms to improve QoR for large FPGA designs and contribute to the end-to-end FPGA compilation flow.

The role requires strong EDA algorithm experience, large-scale optimization, and related FPGA/ASIC flows. Collaboration with routing, timing, and architecture teams is essential, and candidates should have C/C++ skills and hands-on toolchain experience.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 6+ years of experience in FPGA/ASIC CAD, EDA tools, or related fields.
• Experience in algorithms and data structures (optimization, graph theory, heuristics)
• Experience with placement algorithms or physical design flows
• Experience in C/C++ and software engineering best practices
• Experience with placement techniques (analytical placement, simulated annealing, partitioning, clustering)
• Experience with Timing-driven and congestion-driven optimization
• Experience with ASIC or FPGA physical design methodologies
• Experience in solving complex, large-scale optimization problems with high performance and scalability requirements

Responsibilities

• Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
• Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams.
• Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.
• Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs.
• Partner with architecture, routing, and STA teams to align placement strategies with FPGA device capabilities and constraints.
• Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.
• Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.

Skills

C/C++

Algorithms & data structures

FPGA CAD

Parallel algorithms

Education

Bachelor's or Master's degree in Electrical/Computer Engineering or CS

Tools

Quartus

Vivado

Job description

Altera in Toronto, Ontario, is seeking an FPGA Compiler Engineer (Placer) to join our Compiler team. You will design and optimize placement algorithms to improve QoR for large FPGA designs and contribute to the end-to-end FPGA compilation flow.

The role requires strong EDA algorithm experience, large-scale optimization, and related FPGA/ASIC flows. Collaboration with routing, timing, and architecture teams is essential, and candidates should have C/C++ skills and hands-on toolchain experience.