FPGA Design & Validation Engineer – 4G 5G Radio (35952)

Myticas Consulting Inc.; Ottawa; On-site; CAD 90,000 - 130,000; Full time

Job summary

Myticas Consulting Inc. is seeking an FPGA Design & Validation Engineer to support the design, development, verification and validation of 4G/5G Radio Units, focusing on datapath and high-speed interfaces in Kanata, Ottawa.

You will architect FPGA IPs, develop RTL in Verilog/SystemVerilog, and drive verification plans with UVM, collaborating with radio and software teams to meet performance and cost targets.

Qualifications

• Proven FPGA design and RTL development experience.
• Expertise in NR, LTE, eCPRI, CPRI and PTP protocols with signal processing.
• Strong understanding of 4G/5G Radio architecture and O-RAN ecosystem.

Responsibilities

• Define and develop FPGA IP architecture for 4G/5G RUs.
• Create RTL blocks using Verilog/SystemVerilog or VHDL and integrate into systems.
• Define verification plans using UVM and perform simulations and validation.
• Collaborate with Radio Unit teams and software engineers to ensure HW/SW interoperability and lead technical reviews.

Skills

FPGA design

RTL development

4G/5G NR

O-RAN ecosystem

HDL languages

UVM verification

Git version control

SystemVerilog

Verilog

PCIe/Serdes

Tools

Quartus

Vivado

MATLAB/Simulink

HDL Coder

Job description

3 days onsite per week required; no exceptions

FPGA Design & Validation Engineer – 4G/5G Radio Units

Kanata, Ottawa, Ontario — Innovation Drive

Work Arrangement

Minimum 3 days onsite per week required; no exceptions

Contract Term

12 months, with a potential additional 12-month extension

Hours

8 hours per day

Start Date

ASAP

About The Role

We are seeking an FPGA Design Engineer to support the design, development, verification and validation of 4G/5G Radio Units (RUs), with a focus on the datapath.

You will develop FPGA IP architecture, implement complex RTL blocks and validate integrated systems. The role requires strong knowledge of wireless signal processing, radio architecture and high-speed interfaces, along with the ability to solve complex technical problems independently and guide engineering teams.

Key Responsibilities

FPGA Design and Architecture

• Develop FPGA IP architecture for 4G/5G Radio Units.
• Contribute to system-level designs aligned with 3GPP and O-RAN Alliance specifications.
• Define system requirements and functional specifications with limited direction.
• Evaluate design approaches, industry trends and competing solutions to inform product development and long-term technical planning.

RTL Development and Implementation

• Develop complex RTL blocks using Verilog, SystemVerilog or VHDL and integrate them into larger systems.
• Optimize FPGA resource utilization and achieve timing closure.
• Establish technical standards and make design, component and supplier choices that support performance and product cost targets.
• Contribute technical research and evaluations to project plans, budgets, new products and product updates.

Verification and Validation

• Define and execute verification plans using UVM and advanced verification techniques.
• Perform simulations and system-level FPGA validation.
• Identify and resolve complex design, integration and validation issues.

Collaboration and Technical Leadership

• Collaborate with Radio Unit development teams to support system integration.
• Work with software engineers to ensure hardware-software interoperability.
• Provide technical guidance, mentor junior engineers and participate in design reviews.
• Lead technical work on critical projects and communicate progress, risks and recommendations to senior management.
• Incorporate customer input and help resolve internal and external technical issues.

Required Qualifications

• Proven experience in FPGA design and RTL development.
• Expertise in NR, LTE, eCPRI, CPRI and PTP protocols, along with signal processing.
• Strong understanding of 4G/5G Radio architecture and the O-RAN ecosystem.
• Familiarity with JESD204B/C, Ethernet, PCIe, AXI and high-speed SERDES.
• Experience with Quartus, Vivado, MATLAB/Simulink and HDL Coder.
• Knowledge of UVM and verification methodologies.
• Experience with Git/GitHub and version control workflows.
• Ability to work independently, solve complex engineering problems and provide technical leadership.

Preferred Qualifications

• 7+ years of FPGA design experience in wireless or high-speed systems.
• Experience developing high-volume wireless products and FPGA IP.
• Contributions to standards bodies or technical forums, including O-RAN and 3GPP.