Design Verification Engineer

MindSource; Ottawa; On-site; CAD 80,000 - 120,000; Full time

Job summary

A leading company in the tech industry seeks a skilled engineer for a 12-month contract role. You'll develop and maintain verification tests using UVM and lead technical efforts in IP development. Bring your expertise in C/C++, SystemVerilog, and a proven track record in functional verification to thrive in this challenging position.

Qualifications

• 5+ years of experience required.
• Proficiency in C / C++ is essential.
• Experience with SystemVerilog and UVM preferred.

Responsibilities

• Develop and maintain tests for functional verification with UVM.
• Build testbench components for next-generation IP.
• Lead IPs in Control Fabric and provide technical support.

Skills

C / C++

SystemVerilog

UVM

Scripting

Education

Bachelor's degree in computer engineering or electrical engineering

Job description

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Duration : 12 Months

Job Type : Contract

Work Type : Onsite

Key Responsibilities :

• Develop and maintain tests for functional verification with UVM verification at the subsystem level.
• Build testbench components to support the next-generation IP.
• Maintain or improve current test libraries to support IP-level testing.
• Technically lead IPs in Control Fabric.
• Have exposure to AXI protocol and Bootcode Verification.
• Provide technical support to other teams.

Preferred Experience :

• 5+ years of experience required.
• Proficiency in C / C++.
• Experience with SystemVerilog and UVM.
• Scripting knowledge in Perl, Ruby, and Makefile.
• Familiarity with SystemVerilog and modern verification libraries like UVM.

Academic Credentials :

• Bachelor's (required) or Master's degree in computer engineering or electrical engineering.