Design Verification Engineer

Bilinguallink; London; Hybrid; CAD 76,000 - 90,000; Full time

Job summary

Bilinguallink in Markham, ON is seeking a Design Verification (DV) Engineer with ASIC/SoC experience and hands-on AI workflow development. You will build AI agents, skills, and workflows to automate DV tasks and improve productivity across design, verification, and reporting.

The role supports remote-friendly, 6-month engagements with potential extension and conversion to full-time, and offers a competitive $55–$65 per hour on T4.

Qualifications

• 5+ years of experience in Design Verification (DV), ASIC, or SoC development.
• Strong RTL, UVM, simulation, regression, coverage, and chip development workflows.
• At least 6+ months of hands-on experience building AI Agents, Skills, Sub-Agents, and Agentic Workflows.
• Experience with prompt engineering and context engineering for engineering use cases.
• Strong Python scripting and automation skills.
• Experience integrating AI solutions with engineering tools, repositories, and documentation systems.
• Ability to independently design and deliver practical AI productivity solutions.

Responsibilities

• Build and deploy AI agents, skills, sub-agents, and workflow automations for DV and ASIC engineering teams.
• Create reusable AI assets that improve engineering productivity across design, verification, debug, coverage analysis, and reporting.
• Develop agentic workflows using tools such as Codex, Claude Code, MCP frameworks, RAG, and LLM-based systems.
• Automate engineering processes, documentation analysis, test-plan reviews, debug workflows, and reporting.
• Collaborate with DV, Design, CAD, and Engineering teams to identify and implement automation opportunities.
• Help establish scalable AI infrastructure and best practices for long-term engineering use.

Skills

DV Experience

ASIC/SoC

RTL

UVM

Python

AI workflows

AI assets

Prompt engineering

Agentic workflows

Tools

Codex

Claude Code

MCP frameworks

RAG

LLM-based systems

Job description

Title: DV Engineer with AI workflow

Location: Markham, ON location people are preferred but remote is fine

Duration: 6 months with possible extension and conversion to FTE

Pay range: $55/hr to $65/hr on T4

Overview

Seeking a Design Verification (DV) Engineer with strong semiconductor experience and recent hands-on expertise building AI-driven engineering workflows, agents, skills, and automation solutions. The ideal candidate understands ASIC/SoC development and can identify opportunities to automate engineering processes using LLMs, agentic workflows, and reusable AI assets.

Key Responsibilities

• Build and deploy AI agents, skills, sub-agents, and workflow automations for DV and ASIC engineering teams.
• Create reusable AI assets that improve engineering productivity across design, verification, debug, coverage analysis, and reporting.
• Develop agentic workflows using tools such as Codex, Claude Code, MCP frameworks, RAG, and LLM-based systems.
• Automate engineering processes, documentation analysis, test-plan reviews, debug workflows, and reporting.
• Collaborate with DV, Design, CAD, and Engineering teams to identify and implement automation opportunities.
• Help establish scalable AI infrastructure and best practices for long-term engineering use.

Required Qualifications

• 5+ years of experience in Design Verification (DV), ASIC, or SoC development.
• Strong understanding of RTL, UVM, simulation, regression, coverage, and chip development workflows.
• At least 6+ months of recent hands-on experience building:
• AI Agents
• Skills Files
• Sub-Agents
• Agentic Workflows
• Workflow Automation Solutions
• Experience with prompt engineering and context engineering for engineering use cases.
• Strong Python scripting and automation skills.
• Experience integrating AI solutions with engineering tools, repositories, and documentation systems.
• Ability to independently design and deliver practical AI productivity solutions.

Preferred Qualifications

• Hands-on experience with Codex, Claude Code, MCP-based architectures, RAG, and AI orchestration frameworks.
• Experience creating reusable AI solutions for engineering teams.
• Familiarity with enterprise AI deployments and engineering knowledge systems.

Ideal Candidate

A DV Engineer who understands how chips are designed and verified, and has successfully used AI, agents, skills, and workflow automation to improve engineering productivity. Someone who can bridge semiconductor workflows and AI technologies to build reusable solutions adopted across engineering teams.