CPU DFT Engineer

NUVACORE; Markham; Presencial; CAD 198.000 - 354.000; Jornada completa

Descripción de la vacante

Nuvacore is building high-performance, low-power CPU ICT for next-generation compute workloads. As a CPU DFT Engineer you will participate in pre- and post-silicon activities, defining DFT architecture and verification plans while collaborating across design, STA, and PD teams to ensure robust test content for silicon bringup.

You will develop scan/BIST flows, review third-party IPs, and contribute to MBIST strategies, with strong emphasis on JTAG/IEEE standards and RTL debugging.

Formación

• BS or MS in Electrical Engineering with 7 years in DFT or DFT verification.
• Experience with scan or MBIST flows and industry standard EDA tools.
• For scan role, define scan insertion, scan compression, and test modes.
• For MBIST role, familiar with memory repair and interaction with operation.
• Strong understanding of JTAG, IEEE 1500 and IEEE 1687.
• Experience with Verilog RTL and gate level simulations.
• Strong communication and cross-functional collaboration.

Responsabilidades

• Defining and implementing area and power-efficient DFT architecture with design teams.
• Develop scan and BIST insertion flows, implement DFT registers in blocks.
• Complete DFT architecture specifications.
• Review and integrate third-party IPs into DFT architecture.
• Define verification plans for DFT features.
• Review DFT coverage for scan and MBIST.
• Verify DFT features in RTL and gates, and power-aware simulations.
• Generate test content for silicon bringup and support yield analysis.

Conocimientos

DFT engineering

DFT verification

JTAG

IEEE 1500

IEEE 1687

Verilog RTL

Gate level nets

Educación

BS or MS in EE

Herramientas

EDA tools

MBIST tooling

Perl scripting

Python scripting

TCL scripting

Descripción del empleo

Full-time - Multiple Levels - Austin and Santa Clara

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As DFT engineers within the CPU team you will be responsible for test related pre-silicon and post-silicon activities. We will be delivering a DFT architecture which aligns with the projects industry leading power, performance, and area.

THE ROLE

As a CPU DFT Engineer, you will participate in the following areas:

• Defining and implementing area and power efficient DFT architecture while collaborating with design, STA and PD
• Develop scan and BIST insertion flows, implement DFT registers in design blocks
• Completing DFT architecture specifications
• Review and integrate third party IPs into DFT architecture
• Define verification plans for DFT features
• Review DFT coverage for scan and MBIST
• Verification of DFT features in RTL and gates, and power aware simulations
• Generate test content for silicon bringup, and support silicon bringup activities including yield analysis

REQUIREMENTS - MUST TO HAVE

• BS or MS with 7 years experience in DFT or DFT verification
• Scan or MBIST with industry standard EDA tools, or experience with DFT verification flows
• For scan role, able to define scan insertion, scan compression, and clking requirements, and define intest and extest modes
• For MBIST role, be very familiar with memory repair, and repair interaction with functional operation
• Strong understanding of JTAG, IEEE 1500 and IEEE 1687
• Experience with Verilog RTL and gate level netlists, including running and debugging simulations
• Strong communication skills and ability to work with cross functional teams

REQUIREMENTS - NICE TO HAVE

• Using DFT features to support system debug
• Leveraging AI tools to accelerate DFT work flows
• Porting test content and supporting silicon bringup on ATE platforms
• Experience in perl, python, or TCL

$140,000 - $250,000 a year