Staff Digital Verification Engineer-Lead Role

Renesas Electronics; Toronto; Remote; CAD 100,000 - 140,000; Full time

Job summary

A leading semiconductor company is seeking a Staff Digital Verification Engineer. The role involves verifying mixed-signal ASICs using SystemVerilog UVM, implementing test cases, debugging, and mentoring less experienced engineers. Candidates should possess significant industry experience and a strong educational background in engineering.

Qualifications

• 8+ years of practical experience in design verification.
• Experience with functional coverage-driven verification.
• Experience contributing to verification plans.

Responsibilities

• Verification of mixed-signal ASICs in a SystemVerilog UVM environment.
• Implementing test cases based on functional specifications.
• Leading verification efforts for small projects.

Skills

Design verification

SystemVerilog UVM

Debugging

Mentoring

Scripting (Python)

Education

Bachelor’s degree in Electrical, Computer, or Software Engineering

Tools

Synopsys simulation tools

Cadence simulation tools

Unix/Linux environments

Job description

Our Ottawa office is looking for a talented Staff Digital Verification Engineer to join our team. The position is open to remote work within Canada, with a strong preference for candidates in Montreal, Ottawa, and Toronto. After joining, you will be involved in developing industry-leading mixed-signal Application Specific Integrated Circuits in a flexible work environment. You will be part of a growing design and verification team, providing an opportunity to make a significant impact. As a member of the verification team, your responsibilities will include improving and maintaining our UVM test environment, creating new test cases, and debugging mixed-signal chips in digital simulation.

Responsibilities:

• Verification of mixed-signal ASICs in a SystemVerilog UVM environment.
• Implementing test cases based on functional specifications and test plans.
• RTL and possibly gate-level debugging of mixed-signal ASICs.
• Implementing functional coverage and assisting designers in reviewing code coverage.
• Leading verification efforts for small projects.
• Mentoring less experienced engineers.

Qualifications:

• Bachelor’s degree or equivalent in Electrical, Computer, or Software Engineering.
• 8+ years of practical experience in design verification using SystemVerilog UVM and ASIC verification.
• Experience with functional coverage-driven verification sign-off.
• Experience contributing to verification plans.

Preferred Skills:

• Knowledge of PLLs.
• Experience with Synopsys and/or Cadence simulation tools.
• Ability to work in Unix/Linux environments.
• Proficiency in scripting languages such as Python.
• Experience with mixed-signal design modeling and debugging.

Company Description:

Renesas is a leading global semiconductor company committed to developing a safer, healthier, greener, and smarter world. We aim to make every endpoint intelligent by providing innovative product solutions across automotive, industrial, infrastructure, and IoT markets. Our portfolio includes world-class MCUs, SoCs, analog, and power products. We are a key supplier to many of the world's leading electronics manufacturers. With approximately 21,000 employees across more than 30 countries, we embody a culture of transparency, agility, innovation, and entrepreneurship. Renesas values diversity and inclusion, striving to build a sustainable future where technology enhances everyday life. Join us and be part of the future of electronics and technology.