Verification Engineer - Senior (CAN)

ObjectWin Technology; Markham; On-site; CAD 80,000 - 120,000; Full time

Job summary

A leading technology company is seeking a Verification Engineer in Markham. The role involves collaborating with architects and designers to ensure full functional, performance, and power verification closure on digital design blocks. Candidates should have extensive experience in verification methodologies and a solid understanding of digital design concepts.

Qualifications

• 5+ years of verification experience on large ASIC development projects.
• Solid understanding of Computer Architecture and Digital Design concepts.
• Strong background in Verilog, System Verilog, C/C++.

Responsibilities

• Achieve verification closure within project schedules.
• Develop and execute test and coverage plans.
• Create and debug testbenches for design verification.

Skills

Analytical skills

Communication

Collaboration

Attention to detail

Education

Bachelor's degree in Computer Engineering

Master's degree in Computer Engineering (preferred)

Job description

Description:

Location: Markham, ON.

THE ROLE:
As a member of verification team, you will work with leading industry tools and design & verification concepts to achieve full functional, performance & power verification closure on a variety of digital design blocks which are a part of the Graphics Core IP (GFXIP). You will work closely with architects, designers and other design verification engineers to author testplan for pre-silicon verification, planning & development of testbenches to exercise the design, write detailed testplans to cover new blocks and features, drive the development of test-cases and coverpoints or assertions to achieve verification closure.

THE PERSON:
Besides a passion for modern, complex processor architecture, digital design, and verification in general, these personal qualities are essential to success in this role:
Excellent analytical and organizational skills; Outstanding verbal & written communication;
A self-starter who excels at driving tasks to completion and enabling collaboration amongst team members

KEY RESPONSBILITIES:
• Work closely with the architect, RTL designers and other verification engineers to achieve verification closure within project schedules;
• Be responsible for functional, power and performance verification of a block, including verification planning, execution and DV closure;
• Develop and execute test and coverage plans to ensure the functional, performance and power completeness;
• Create, reuse and debug testbenches, verification components and tests for verification of the design;
• Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.

EXPERIENCE AND EDUCATION:
• Minimum 5+ years of verification experience on large ASIC development projects;
• Solid understanding of Computer Architecture and Digital Design concepts;
• Very strong background in Verilog, System Verilog, C/C++/OOO coding techniques;
• Experience working with UVM, OVM or equivalent;
• Experience with constrained random verification, functional coverage and assertions;
• Experience with formal verification is an added advantage;
• Familiarity with one of the scripting languages: perl/tcl/ruby/Bash/python;
• Experience working with industry standards tools such Synopsys VCS, VC Formal, DVE, Verdi, GDB or equivalent;
• Strong analytical skills and attention to detail;
• Bachelor's (or preferably Master's) degree in Computer Engineering, Computer Science, Electrical Engineering or similar
tests and plan