ASIC Digital Design, Sr Staff Engineer

Synopsys, Inc.; Ontario; On-site; CAD 125,000 - 150,000; Full time

Job summary

An established industry player is seeking a PHY architect to join their innovative architecture team. This exciting role involves collaborating with senior architects to design next-generation UCIe and HBM PHYs. You will leverage your expertise in computer architecture and mixed-signal design to create cutting-edge products. The position offers the opportunity to work within a dynamic team, addressing customer needs and driving product development. If you are passionate about high-speed interfaces and thrive in a collaborative environment, this role could be the perfect fit for you.

Qualifications

• 8+ years of experience in related fields or advanced degree with 6+ years.
• Strong understanding of mixed-signal design and off-chip signaling.

Responsibilities

• Translate customer requirements into product design features.
• Generate functional descriptions and specifications for products.
• Support customers in product implementation.

Skills

Mixed-signal design

Off-chip signaling

RTL development

Design-for-test

Logical verification

Troubleshooting and debugging

High-speed interface principles

Education

Bachelor's degree in Engineering

Master's degree in Engineering

Job description

We’re looking for a PHY architect to join the UCIe/HBM PHY architecture team. Does this sound like a good role for you?

In this position, you will be part of an architecture team that plans and executes the design for the next-generation UCIe and HBM PHYs in the Synopsys IP portfolio. The job entails working with senior architects to understand standard specifications, evaluate ideas, draft specifications, and enable a larger team of design engineers bringing new ideas into silicon. You’d leverage your understanding of computer architecture, mixed-signal design, off-chip signaling, RTL development, design-for-test, and logical verification to create leading-edge products. Supporting Synopsys’ customers is also an important part of the role. You will join a collaborative, multi-person engineering team engaged in similar activities on related UCIe and HBM PHY development projects.

Job Responsibilities:

1. With the guidance of a senior architect, understand marketing, customer desires and standard specification and translate those into a set of product design features and functions of ongoing and future designs to create best-in-class products.
2. Generate the functional description for the product, creating specifications describing the interface components, operation, structure, and behavioral parameters.
3. Develop models representing the performance features of interface design sub-components.
4. Solve design execution problems tied to the product definition.
5. Perform feasibility studies through the evaluation of trial designs.
6. Document results, conclusions, and technical insights into performance, power, area, and functional parameters.
7. Interact and communicate with design teams performing digital design and verification, analog circuit design and verification, and layout design.
8. Support customers in their implementation of the product.

Key Qualifications and Experience:

1. Possesses a minimum of 8+ years of related experience or an advanced degree with 6+ years of related experience.
2. Understands high-speed interface principles, such as mixed-signal design and off-chip signaling.
3. Skilled in generating and supporting documentation through written specifications, and communicating those specifications within a design team and to external customers.
4. Well-versed in RTL logic design, simulation, test planning, and verification of complex integrated circuit components.
5. Knowledgeable in design-for-test, timing analysis, power analysis, behavioral modeling, and synthesis constraints.
6. Able to work across a multi-site team to communicate ideas, understand problems, and find solutions to create a leading-edge design.
7. Skilled in troubleshooting and debug of mixed-signal interfaces.
8. Knowledge in UCIe and HBM protocols and JEDEC spec is a plus.
9. Able to work autonomously with high-level guidance.