Senior Fpga Developer

Caderno Nacional; São Paulo; Presencial; BRL 350 000 - 550 000; Tempo integral

Resumo da oferta

A Caderno Nacional procura um engenheiro FPGA sênior para liderar a arquitetura de FPGA de nossos produtos de teste e medição de comunicações. O profissional definirá a estratégia de design, trade-offs de IP e fluência de ferramentas para atender requisitos de alto desempenho.

Responsável por fechar timing, orientar a equipe de FPGA e resolver problemas complexos de debug de interfaces, incluindo SFP/QSFP e protocolos de rede, com foco em qualidade e entrega em prazos agressivos.

Qualificações

• Formação mínima em Engenharia Elétrica e/ou de Computação com forte foco em FPGA.
• Experiência de 12–15 anos, com pelo menos 5 anos fechando timing em designs multi-Gbps.
• Domínio de Verilog/SystemVerilog e/ou VHDL; excelente capacidade de debug e validação.

Responsabilidades

• Definir e conduzir a arquitetura end-to-end de FPGA, incluindo trade-offs de IP, floorplanning e estratégia de timing para designs multi-Gbps.
• Atuar como ponto de escalonamento técnico para questões de FPGA, orientar engenheiros e liderar debug de silicon e bring-up de placas.
• Conduzir fechamentos de timing, análise de link e debug de problemas de interface Ethernet de alto desempenho; colaborar com equipes globais.

Conhecimentos

HDL design

FPGA transceivers

Timing closure

Hard IP & PLLs

Ethernet 10G+

UVM verification

Git

Mentoring

HW/FW architecture

Formação académica

Bacharelado/Mestrado em Engenharia Elétrica e/ou de Computação

Ferramentas

Altera toolchains

Xilinx toolchains

Descrição da oferta de emprego

Segmento: Não Informado

Atividades: A leader in light management technologies for 3D sensing, anti-counterfeiting, consumer electronics, industrial, automotive, government and aerospace applications. Employees working on this project are passionate about supporting customer success and we welcome people who bring their best every day to the company – to question, to collaborate and to push for solutions that will delight our customers.

About the Role

We are seeking a Principal/Staff-level FPGA Engineer — a recognized technical authority — to own FPGA architecture for our state-of-the-art Communications Test & Measurement products.

Responsibilities

• The successful candidate will define and drive end-to-end FPGA architecture, including make/buy tradeoffs on IP, floorplanning and timing closure strategy for multi-gigabit designs, and DFX approach, using Verilog/SystemVerilog/VHDL and industry-leading simulation, synthesis, place-and-route, and formal/UVM verification tools.
• This person will serve as the final technical escalation point for FPGA design and debug issues across the team, mentor other FPGA engineers, and lead root-cause debug of silicon and board bring-up issues that could not be resolved elsewhere.

Qualifications

• BS or MS degree in Electrical and/or Computer Engineering with a minimum of 12-15 years of relevant experience, including at least 5+ years specifically architecting and closing timing on multi-Gbps SerDes/transceiver-based FPGA designs.

Required Skills

• Demonstrated expertise architecting and implementing high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL required.
• Deep, hands-on expertise with FPGA transceivers, hard IP, and PLLs — including timing closure, equalization, and link debug at multi-Gbps rates — required (not incidental exposure).
• Demonstrated experience closing timing and debugging link-layer issues on high-speed Ethernet (10M to 1.6T) and IP protocol stacks in production designs.
• Proven expertise with optical interfaces and modules (SFPs, QSFPs) in shipped products.
• Deep working knowledge of VLANs, MPLS, VPLS, and Voice/Video over IP (VoIP, IPTV).
• Extensive experience with AMD or Altera FPGA devices and their full implementation toolchains, including advanced timing closure and floorplanning techniques.
• Proven experience with formal verification and/or UVM-based verification methodologies, not limited to directed testbenches.
• Demonstrated track record of taking FPGA designs from architecture through volume production, including systems-level tradeoffs across the HW/FW boundary.
• Version control experience using Git or similar tools.
• Exceptional written and oral communication skills, including the ability to mentor engineers and communicate architecture decisions with stakeholders across the world.
• Exceptional analytical and organizational skills, with an uncompromising commitment to accuracy and technical rigor in a fast-paced product environment.

Preferred Skills

Languages: English: B2 Upper Intermediate

Dias da Semana: Não Informado

Horário / Período: Não Informado