Senior Physical Design Engineer

EnSilica Plc; Campinas; Presencial; BRL 223 200 - 334 800; Tempo integral

Resumo da oferta

A growing semiconductor company is seeking an experienced ASIC Implementation Engineer for its Campinas office in Brazil. The role requires a strong academic background and at least 5 years in IC Physical Design, particularly in digital ASIC development. The ideal candidate will excel in ownership of the RTL-to-GDSII flow, collaborate with cross-functional teams, and maintain the highest quality standards in projects. Flexibility for international travel may be required.

Qualificações

• 5+ years’ experience in IC Physical Design in advanced digital ASIC development.
• Strong academic record from a Tier 1 group University.
• Ability to quickly solve problems efficiently.

Responsabilidades

• Take ownership of RTL-to-GDSII implementation flow.
• Collaborate with teams to ensure quality deliverables.
• Maintain and improve EDA tool flows as needed.
• Stay updated on advanced ASIC implementation methodologies.

Conhecimentos

Physical Design (PD)

Digital ASIC development

RTL to GDSII implementation

Solid hands-on experience with Synopsys ICC or Cadence Innovus

STA and timing closure

Power-management implementation

Power-rail analysis and verification

RC extraction flows

DRC/LVS/ERC/DFM

Formação académica

1st or 2.1 in Electronics, Physics or relevant subject

Ferramentas

Synopsys ICC

Cadence Innovus

Mentor tools

Synopsys tools

Descrição da oferta de emprego

This role is based in our Campinas office in Brazil.

As part of our ongoing expansion, EnSilica need to strengthen our ASIC Implementation team. We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business.

The ideal candidate will have a strong academic record and 5+ years experience in IC Physical Design (PD) within advanced digital ASIC development flows.

You will be familiar with the challenges of implementing complex ASIC/SoC designs from RTL to tapeout-ready GDSII in process nodes down to at least 12FF.

Key Responsibilities

• Take full-flow ownership of all stages of the digital RTL-to-GDSII implementation flow for complex ASIC block-level
• Work closely with other EnSilica teams to deliver projects on-time and to the required quality levels
• Maintain and contribute to improve EDA tool flows, as needed, for each stage of the development flow
• Keep up to date with all aspects of advanced ASIC implementation methodology and best-practice to ensure that EnSilica’s expertise and services are always current and appropriate for each customer project

Key Skills and Experience

• 1st or 2.1 Electronics, Physics or relevant subject from a Tier 1 group University
• 5+ years’ experience in industry with a strong track record in Physical Implementation gained across several successful ASIC projects, and at process nodes at least down to and including 16FF
• Specific skills:
  • Solid hands-on experience with either Synopsys ICC* or Cadence Innovus for block-level and (ideally) full-chip design, ideally down to 16FF or below
  • STA and timing closure, including constraint development and verification
  • Power-management implementation using UPF/CPF, including verification and power estimation
  • Power-rail analysis and verification
  • Setup and use of RC extraction flows
  • Ability to setup and run DRC/LVS/ERC/DFM using either Mentor or Synopsys tools
• Ability to quickly and efficiently solve problems, working together with our technical leaders and/or with support from our suppliers and customers where needed

Personality

• Excellent communication and interpersonal skills.
• Strong and effective presentation skills, able to operate at multiple levels including senior management.
• Self-motivated achiever who gains satisfaction from providing excellent customer service and has a ‘can-do’ attitude.
• Happy to take ownership of problems and provide suitable solutions.
• Creative problem solving.
• Team player.
• Ability to work in a dynamic environment.

Position Specifics

This role is flexible, some international travel may be required.