Lead Product Engineer: SoC Verification

Cadence Design Systems; Belo Horizonte; On-site; BRL 216,000 - 384,000; Full time

Benefits offered by this job

Competitive benefits

Job summary

Cadence Design Systems in Belo Horizonte, Brazil seeks a Lead Product Engineer: SoC Verification to deploy Portable Stimulus methodologies across complex SoC programs. You will work with semiconductor design and verification teams to debug issues and refine verification approaches in real production environments.

The role spans verification methodology, system architecture, and EDA product engineering, with collaboration across Cadence R&D and field teams to advance AI-assisted verification

Qualifications

• Bachelor's degree in Computer Science or related areas.
• Experience in SoC verification, validation, or verification methodology.
• Strong hands-on experience with SystemVerilog and UVM or embedded/bare metal environments.
• Solid understanding of constrained-random verification and system-level test generation.
• Experience debugging complex verification environments.
• Strong programming or scripting skills (C/C++/Python or similar).

Responsibilities

• Deploy Portable Stimulus methodologies in complex SoC programs.
• Debug generation and solver issues involving constraints, resources, execution ordering, and scenario realization.
• Investigate modeling challenges in large system-level PSS environments.
• Collaborate with Cadence R&D to diagnose tool issues and improve PSS features.
• Define and refine methodologies for scalable system-level verification.
• Develop reference models and best practices for customers and field teams.
• Support advanced system-level verification use cases including software-driven verification, device programming, reuse across simulation, emulation, and post-silicon, plus integration with virtual platforms.
• Contribute to emerging AI-assisted verification flows built around PSS models.

Skills

SoC verification

SystemVerilog

UVM

Constrained-random verification

Programming/scripting: Python/C/C++

Education

Bachelor's degree in Computer Science or related areas

Tools

SystemVerilog

UVM

C/C++

Python

Job description

Lead Product Engineer: SoC VerificationSkip to main content#Lead Product Engineer: SoC Verification page is loaded## Lead Product Engineer: SoC VerificationApplylocations: BELO HORIZONTEtime type: Full timeposted on: Posted Todayjob requisition id: R54050## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**Cadence Design Systems Inc. is looking for a motivated **Lead Product Engineer: SoC Verification** to work with us in Belo Horizonte, Brazil for **Perspec** Team. **Perspec** is Cadence’s Portable Stimulus solution used by leading semiconductor companies to solve complex **SoC and system-level verification challenges**.This role sits at the intersection of **verification methodology, system architecture, and EDA product engineering**. You will work directly with advanced verification teams at major semiconductor companies to deploy **Portable Stimulus (PSS)** in real production environments and help drive the evolution of Perspec.The work spans **formal languages**, **simulation, emulation, virtual platforms, firmware-driven verification, and post-silicon reuse**, and increasingly involves **AI-assisted verification workflows**.Portable Stimulus is changing how system-level verification is done.In this role you will work on **real verification problems at scale**, interacting with some of the most advanced verification teams in the industry and helping shape how **hardware/software co-verification** is done across simulation, emulation, and silicon. If you enjoy **deep technical problem solving, modeling complex systems, and working close to both customers and EDA tool development**, this is a unique role.Cadence has been nominated as a Great Place to Work globally and in Brazil, and is also a Fortune 100 Best Companies to Work For. **Job Description:*** Work directly with semiconductor design and verification teams to deploy **Portable Stimulus methodologies** in complex SoC programs.* Help debug difficult generation and solver issues involving **constraints, resources, execution ordering, and scenario realization**.* Investigate real-world modeling challenges that arise in **large system-level PSS environments**.* Collaborate closely with **Cadence R&D** to diagnose tool issues, influence new features, and improve PSS standard* Help define and refine **methodologies for scalable system-level verification**.* Develop reference models, internal knowledge, and best practices used by both customers and Cadence field teams.* Support advanced system-level verification use cases including: + software-driven verification + device programming flows + reuse between simulation, emulation, and post-silicon + integration with virtual platforms and firmware environments* Contribute to emerging **AI-assisted verification flows** built around PSS models. **Requirements:*** Complete Bachelor's degree in Computer Science or related areas.* Experience in **SoC verification, validation, or verification methodology*** Strong hands-on experience with **SystemVerilog and UVM**or **embedded / bare metal environments*** Solid understanding of **constrained-random verification and system-level test generation*** Experience debugging complex verification environments* Strong programming or scripting skills (C/C++/Python or similar)* Ability to work directly with engineering teams to solve difficult technical problems **Nice to Have:*** Exposure to **Portable Stimulus (PSS)** or interest in learning it* Experience with **Perspec or other PSS tools*** Experience working with complex SoC subsystems and protocols such as **PCIe, DDR, networking**, or **ARM-based SoCs*** Experience with **embedded software programming and bare-metal environments*** Familiarity with **emulation, virtual platforms, or post-silicon validation*** Experience developing **verification methodology or reusable verification libraries** ## **Additional Job Details:*** Employment category: CLT.* Employment term: 40 hours/week.* Competitive benefits.* Location: Av Contorno 5800, Belo Horizonte, Minas Gerais, Brazil.