Senior Digital ASIC Engineer – Hybrid (Medical Devices)

C43 Cochlear Technology Centre Belgium (Belgium); Antwerpen; Hybrid; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Flexible benefits

Comprehensive onboarding program

Hybrid work options

Job summary

Cochlear is seeking a Senior Digital ASIC Engineer in Mechelen with hybrid work options. You will contribute to ASIC roadmaps, develop RTL and verification activities, and collaborate with external partners to ensure successful silicon outcomes.

The role emphasizes strong problem solving, detailed design work and cross-functional collaboration. The ideal candidate has 7+ years in digital ASIC/FPGA, experience with SystemVerilog/UVM, clock/reset and low-power design, and a track record of

Qualifications

• 7+ years in digital ASIC/FPGA design, verification or integration.
• Experience with SystemVerilog/UVM and formal verification is preferred.
• Knowledge of clock/reset, CDC/RDC, low-power design, and DFT.

Responsibilities

• Contribute to ASIC technology roadmaps and evaluate component solutions against product needs.
• Develop and review digital ASIC requirements covering functionality, interfaces, performance and power.
• Review architecture, RTL, clock/reset, CDC/RDC, low-power implementation, DFT and verification evidence.
• Collaborate with external ASIC design/verification partners and drive issues to resolution.
• Identify risks using simulation, formal verification, FPGA prototypes and silicon evaluation.
• Support tape-out readiness, silicon bring-up, characterization and debugging.
• Partner with hardware, embedded software and product engineering teams through integration.
• Apply scripting, automation and AI-assisted approaches to improve reviews and testing.

Skills

Digital ASIC design

SystemVerilog/UVM

RTL/verification

Python scripting

Clock/reset/CDC/RDC

DFT/silicon debugging

Problem solving

Education

Master's in Electrical Engineering

Tools

SystemVerilog

UVM

Python

Job description

Cochlear is seeking a Senior Digital ASIC Engineer in Mechelen with hybrid work options. You will contribute to ASIC roadmaps, develop RTL and verification activities, and collaborate with external partners to ensure successful silicon outcomes.

The role emphasizes strong problem solving, detailed design work and cross-functional collaboration. The ideal candidate has 7+ years in digital ASIC/FPGA, experience with SystemVerilog/UVM, clock/reset and low-power design, and a track record of