Digital FE Design Engineer

Euraxess; Heverlee; Sur place; EUR 50 000 - 70 000; Plein temps

Avantages offerts par ce poste

Market-appropriate salary

Fringe benefits

Support for professional development

Résumé du poste

Euraxess in Heverlee, Belgium, is looking for a Digital Front-End Design Engineer to drive the complete RTL-to-GDS flow and shape next-generation silicon solutions. You will ensure high-quality implementation of complex ASIC designs while collaborating with a skilled team.

The ideal candidate should possess 0-2 years of front-end design experience, knowledge of synthesis and DFT, and proficiency in Cadence and Synopsys toolsets. If selected, you'll join a premier research center committed to inclusivity and innovation while receiving a competitive salary.

Qualifications

• 0-2 years of experience in ASIC front-end design.
• Expertise in synthesis, DFT, LEC, ATPG, and test coverage improvement.
• Strong interest in digital design principles.

Responsabilités

• Drive the complete RTL-to-GDS flow for ASIC designs.
• Perform RTL synthesis and optimize timing, area, and power.
• Collaborate with physical design teams for RTL-to-GDS integration.

Connaissances

RTL-to-Netlist flow

Synthesis

Design-for-Test (DFT)

Logical Equivalence Checking (LEC)

Test Pattern Generation (ATPG)

Verilog/SystemVerilog

Tcl

Python

Problem-solving

Communication skills

Formation

Master's degree in electrical or computer engineering

Outils

Cadence tools (Genus, Modus, Conformal, Xcelium)

Synopsys tools (DC, FC, TestMAX, SpyGlass)

Tessent tools for DFT and ATPG

Description du poste

Organisation/Company IMEC Research Field Engineering Computer science Researcher Profile First Stage Researcher (R1) Recognised Researcher (R2) Established Researcher (R3) Leading Researcher (R4) Other Profession Positions Other Positions Application Deadline 18 Sep 2026 - 08:24 (Europe/Brussels) Country Belgium Type of Contract Permanent Job Status Full-time Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure? No

Offer Description

Digital Front-End Design Engineer – Drive the complete RTL-to-GDS flow and shape next-generation silicon solutions.

What you will do

As a Digital Front-End Design Engineer, you are responsible for all design tasks in the RTL-to-GDS flow, ensuring high-quality and efficient implementation of complex ASIC designs. You work within a highly skilled Front-End (FE) team that provides design services to both internal IMEC research groups and external customers worldwide. The team consists of 10 members with diverse experience levels, offering a collaborative environment for knowledge sharing and technical growth.

• Perform RTL synthesis and optimize timing, area, and power.
• Execute DFT (Design-for-Test) insertion using industry-standard tools.
• Conduct Logical Equivalence Checking (LEC) to validate design integrity.
• Generate and validate ATPG (Automatic Test Pattern Generation) patterns.
• Improve test coverage through advanced methodologies.
• Run pre-layout and post-layout test pattern simulations to ensure robustness.
• Collaborate closely with physical design teams for seamless RTL-to-GDS integration.
• Utilize Cadence/Synopsys EDA tools for synthesis, DFT insertion, and ATPG.
• Apply Tessent (Siemens) tools for DFT insertion and ATPG in specific projects.
• Troubleshoot and resolve design issues across the front-end flow.
• Document design processes and contribute to continuous improvement initiatives.
• Engage with internal and external stakeholders to deliver high-quality design services.

You are an ASIC design professional with a strong interest in front-end methodologies and a passion for delivering high-quality silicon. You bring:

• 0-2 years of experience in ASIC front-end design, including RTL-to-Netlist flow. A master’s degree in a related field (electrical or computer engineering) is required for candidates with no industry experience.
• Expertise in synthesis, DFT, LEC, ATPG, and test coverage improvement.
• Hands‑on experience with Cadence (preferred) (Genus, Modus, Conformal, Xcelium, etc.) and/or Synopsys toolsets (DC, FC, TestMAX, SpyGlass, etc.).
• Familiarity with Tessent tools for DFT and ATPG.
• Understanding of and strong interest in digital design principles, timing closure, and test strategies.
• Proficiency in Verilog/SystemVerilog and scripting languages (Tcl, Python, etc.).
• Strong problem‑solving skills and ability to work in cross-functional teams.
• Eagerness to learn and improve.
• Excellent communication skills and attention to detail.

Languages ENGLISH Level Excellent

Additional Information

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.