Senior IC Verification Architect (UVM/SystemVerilog)

Infineon Technologies

Australia

On-site

AUD 180,000 - 240,000

Full time

14 days+
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Job summary

Infineon Technologies Australia is seeking a senior IC verification engineer to lead detailed simulation, verification and validation of complex ASICs. You will design testbenches in SystemVerilog/UVM for functional and power-aware RTL, and build UVM components like agents, scoreboards and environments.

You will drive verification metrics, collaborate with cross-functional teams, and communicate with customers during design reviews and weekly calls to keep schedules and quality on track.

Qualifications

  • Bachelor’s in electrical engineering or equivalent.
  • Proven expertise with UVM and SystemVerilog based verification.
  • Excellent understanding of ASIC verification methodologies and proven experience.

Responsibilities

  • Perform and supervise detailed Simulation, verification and validation of integrated circuits.
  • Develop testbenches using System Verilog and UVM for functional and power aware RTL.
  • Develop UVM components like agents, scoreboards and environments; develop assertions and coverage.
  • Develop test plans, UVM based test sequences and virtual sequencers.
  • Drive closure of verification metrics to cover verification space and close gaps.
  • Provide regression setup and debug RTL and gate level netlists.
  • Review industry specs and augment test plans to improve verification quality.
  • Participate in post-silicon bring up, validation and compliance testing and debug.
  • Collaborate with Product Architect, Designers, Project leads and managers; communicate with customers.

Skills

UVM
SystemVerilog
ASIC verification

Education

Bachelor’s in Electrical Engineering

Tools

Git
Jenkins
Jira

Job description

Infineon Technologies Australia is seeking a senior IC verification engineer to lead detailed simulation, verification and validation of complex ASICs. You will design testbenches in SystemVerilog/UVM for functional and power-aware RTL, and build UVM components like agents, scoreboards and environments.

You will drive verification metrics, collaborate with cross-functional teams, and communicate with customers during design reviews and weekly calls to keep schedules and quality on track.

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