Senior FPGA Engineer - Space Comms (RTL/Bring-Up)

GCS; Redmond; On-site; AUD 214,000 - 300,000; Full time

Job summary

GCS is seeking a Senior FPGA Engineer to join a cutting-edge satellite communications program. You will take designs from concept through RTL development, timing closure, hardware bring-up, and validation in a hands-on lab environment.

This role emphasizes working directly with hardware, implementing high-speed interfaces, and collaborating with cross-functional teams to power next-generation space-grade systems.

Qualifications

• 8+ years FPGA/RTL development experience.
• Proficient in Verilog, SystemVerilog and VHDL.
• Experience with high-speed serial protocols and FPGA transceivers.

Responsibilities

• Design and develop FPGA RTL using Verilog, SystemVerilog, or VHDL.
• Implement and optimize high-speed interfaces including JESD204, PCIe, Aurora, and Ethernet.
• Drive timing closure, clocking architecture, constraints, and performance optimization.
• Perform board bring-up, hardware validation, and debugging using JTAG, ILA, ChipScope, SignalTap, and lab equipment.
• Develop FPGA solutions for high-speed data movement and communications between custom silicon devices.
• Prototype new capabilities for future ASIC development efforts.
• Collaborate closely with board design, systems, validation, and hardware engineering teams.

Skills

FPGA RTL development

Verilog

SystemVerilog

VHDL

Timing closure

Hardware debugging

High-speed serial protocols

FPGA platforms (AMD/Xilinx, Intel/Alte

Tools

JTAG

ILA

ChipScope

SignalTap

Lab equipment

Job description

GCS is seeking a Senior FPGA Engineer to join a cutting-edge satellite communications program. You will take designs from concept through RTL development, timing closure, hardware bring-up, and validation in a hands-on lab environment.

This role emphasizes working directly with hardware, implementing high-speed interfaces, and collaborating with cross-functional teams to power next-generation space-grade systems.