Senior Compiler Engineer

Werben HR; Buenos Aires; A distancia; ARS 146.337.000 - 313.580.000; Jornada completa

Descripción de la vacante

Werben HR is seeking a highly specialized Compiler Engineer for a long-term, fully remote role with US time-zone overlap. You will work with US-based engineers on compiler infrastructure, lowering pipelines, and hardware-targeted optimizations across GPUs, TPUs, FPGAs, and AI ASICs.

The position requires fluent English, strong MLIR/LLVM experience, and advanced C++ in high-performance settings. Daily collaboration with US teams will be in English, with a long-term independent contractor

Formación

• Proven hands-on experience as a compiler engineer.
• Strong experience with MLIR/LLVM infrastructure.
• Advanced C++ in high-performance contexts.
• Ability to optimize compilers for GPU/TPU/FPGA/AI ASICs.
• Fluent English for daily interaction with US teams.

Responsabilidades

• Design, build, and maintain compiler infrastructure using MLIR and/or LLVM.
• Implement lowering pipelines, compiler/graph transformations, and optimization passes.
• Target dynamic hardware platforms by optimizing memory and data movement.
• Collaborate with US engineers and client teams to optimize compiler features.

Conocimientos

Compiler engineering

C++ programming

MLIR/LLVM

Performance optimization

English proficiency

Herramientas

MLIR

LLVM

GPU/TPU/FPGAs knowledge

Descripción del empleo

Location: LATAM (Any country, 100% Remote) Employment Type: Independent Contractor (Long-term) Schedule: US Timezones (PST or CST overlap required)

About the Role

We are seeking a highly specialized Compiler Engineer to join a long-term project working directly with US-based engineering teams. In this role, you will work at the intersection of high-level frameworks and specialized hardware targets. You will be responsible for building, optimizing, and transforming IRs, writing custom optimization passes, and driving compiler pipeline performance.

Key Responsibilities

• Design, build, and maintain compiler infrastructure using MLIR and/or LLVM.
• Implement lowering pipelines, compiler/graph transformations, and specialized optimization passes.
• Target dynamic hardware platforms (GPUs, TPUs, FPGAs, CGRAs, DSPs, or AI ASICs) by optimizing memory hierarchy utilization, scheduling, and data movement.
• Collaborate daily in English with US engineering leads and client teams to architecture compiler features and address performance bottlenecks.

Requirements

• English Proficiency: C1 or higher (fluent spoken and written English required for daily direct interaction with US teams).
• Core Expertise: Proven, hands‑on experience as a genuine Compiler Engineer.
• Frameworks: Strong background working with MLIR and/or LLVM infrastructure.
• Programming: Advanced C++ proficiency in systems‑level/high‑performance contexts.
• Optimization & Targets: Hands‑on expertise in optimizing compilers targeted at specific hardware (GPU, TPU, FPGA, CGRA, DSP, or AI ASICs).
• Technical Concepts: Demonstrated experience with: Intermediate Representations (IRs) Lowering strategies and graph transformations Optimization passes and instruction/task scheduling Memory hierarchy management and data movement optimization.

Important Note on Profile Fit: Candidates coming strictly from Data Science, Applied ML, MLOps, general Backend/C++, FPGA/RTL design, or CUDA/kernel development will not be considered unless they possess concrete, hands‑on experience in compiler engineering.

Interview Process

• Initial Screening: Recruiter interview with the Applica team.
• Technical Validation: Technical assessment focused on compiler fundamentals, MLIR/LLVM, and C++.
• Client Interview: Final technical and team‑fit evaluation with the US client.