VP, Quantum Error Correction & Fault-Tolerant QC Research

Testing Site - JPMC; New York (NY); Presencial; USD 180.000 - 280.000; Jornada completa

Descripción de la vacante

JPMorgan Chase's Global Technology Applied Research (GTAR) center seeks a Vice President quantum computing researcher to develop and optimize fault-tolerant quantum protocols, and to validate them experimentally on quantum hardware.

You will lead research agendas, implement FTQC protocols, and contribute to publications while building reusable codebases for colleagues to run quantum algorithms fault-tolerantly.

Formación

• Ph.D. degree in computer science, physics, math, engineering, or related fields, or equivalent experience, plus at least 2 years of relevant experience (industry or postdoc)
• Fluency with basics of qubit-based stabilizer QEC: stabilizer and subsystem codes; CSS codes; parity check matrices; logical and gauge operators; thresholds and pseudo-thresholds; Clifford and non-Clifford gates; Shor, Steane, and Knill QEC; code distance and effective (circuit) distance
• Experience with analytical and numerical circuit-level investigation of QEC and FTQC: constructing circuits for QEC cycles, state preparation, and logical operations; specifying noise models; building detector error models; running numerical simulations; decoding; computing logical error rates
• Experience in at least one of: designing fault-tolerant gadgets, magic-state distillation or cultivation, generalized code surgery, code adapters and extractors, dynamical codes, ZX calculus
• Experience building quantum circuits in a major software framework such as Cirq, Qiskit, or Pytket
• Fluency in at least one of: Python, Julia, C++, Rust
• Strong oral and written communication skills, strong scientific publication record

Responsabilidades

• Lead a research agenda for advancement and validation of state-of-the-art methods for universal fault-tolerant quantum computation on hardware
• Lead the development of circuit gadgets and protocols for universal FTQC
• Lead the numerical investigation and optimization of fault-tolerant gadgets for real-world execution on hardware
• Lead the implementation and experimental validation of protocols for universal FTQC on hardware
• Document analytical, numerical, and experimental results in scientific papers
• Implement, maintain, and manage a codebase that colleagues can use to run quantum algorithms fault-tolerantly on hardware

Conocimientos

QEC basics

Circuit design

Quantum simulations

Technical writing

Programming languages

Educación

Ph.D. in CS/Physics/Math/Engineering

Herramientas

Cirq

Qiskit

Pytket

Descripción del empleo

JPMorgan Chase's Global Technology Applied Research (GTAR) center seeks a Vice President quantum computing researcher to develop and optimize fault-tolerant quantum protocols, and to validate them experimentally on quantum hardware.

You will lead research agendas, implement FTQC protocols, and contribute to publications while building reusable codebases for colleagues to run quantum algorithms fault-tolerantly.