VLSI Physical Design R&D Engineer (PPA & Optimization)

NVIDIA Corporation; Austin (TX); On-site; USD 136,000 - 219,000; Full time

Job summary

NVIDIA seeks a skilled R&D Software Engineer to advance VLSI physical design algorithms and develop high-performance C++ tools used across internal optimization workflows. You will work on co-optimizing legalization, sizing, and related steps to push chip frequency while reducing power across a broad toolset.

The role requires strong experience in C++ development for VLSI timing optimization and familiarity with leading design flows, along with the aspiration to innovate across hybrid engines

Qualifications

• Masters or PhD in Electrical Engineering or Computer Science (or equivalent).
• Experience with VLSI algorithms development using C++.
• Understanding of VLSI timing optimization and related concepts.
• Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC and typical design flows written in Perl, Tcl, and Python.

Responsibilities

• Invent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.
• Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.
• We as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

Skills

VLSI algorithms development with C++

Multithreading

Distributed computing

Reinforcement learning / ML for design

Education

Masters or PhD in Electrical Engineering or Computer Science

Tools

ICC2

Innovus

PrimeTime

Tempus

StarRC

Perl

Tcl

Python

Job description

NVIDIA seeks a skilled R&D Software Engineer to advance VLSI physical design algorithms and develop high-performance C++ tools used across internal optimization workflows. You will work on co-optimizing legalization, sizing, and related steps to push chip frequency while reducing power across a broad toolset.

The role requires strong experience in C++ development for VLSI timing optimization and familiarity with leading design flows, along with the aspiration to innovate across hybrid engines