SoC Design & Integration Engineer – AI & HPC

QUALCOMM, Inc.; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Benefits offered by this job

Annual discretionary bonus

RSU grants

Benefits package

Job summary

Qualcomm Technologies, Inc. is seeking bright ASIC engineers to join the SoC team responsible for RTL Design, flows and methodology for high performance ASICs in cutting-edge compute and AI spaces.

The role emphasizes strong teamwork, architecture and verification discipline, and opportunities to work on new architectures for advanced devices. Ideal candidates will have a background in server/data center IPs, learning IPs, and power/speed optimization, with experience across ASIC development and

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 2+ years of ASIC design/verification experience.
• Master's degree in Science, Engineering, or related field with 1+ year of ASIC design/verification experience.
• PhD in Science, Engineering, or related field.

Responsibilities

• Hands-on: uses tools to execute SOC architecture and design per design protocol.
• Resolve architecture, design, or verification problems with ASIC engineering practices.
• Execute design and verification strategies for ASICs, SoC, and IP cores.
• Participate in design and architecture reviews and demonstrate analytical skills.
• Identify flow and process improvements through design techniques and automation.
• Communicate effectively within the team and with peer teams.
• Collaborate with teammates to achieve common goals and share learnings.

Skills

Server/Data Center IPs

ML IPs design

Speed/Power optimization

Architecture/verification oversight

System simulation

Automation scripting

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

RTL Design Tools

SystemVerilog/Verilog

Job description

Qualcomm Technologies, Inc. is seeking bright ASIC engineers to join the SoC team responsible for RTL Design, flows and methodology for high performance ASICs in cutting-edge compute and AI spaces.

The role emphasizes strong teamwork, architecture and verification discipline, and opportunities to work on new architectures for advanced devices. Ideal candidates will have a background in server/data center IPs, learning IPs, and power/speed optimization, with experience across ASIC development and