VHDL FPGA Digital Engineer | Secret Clearance

PDS Defense, Inc.; San Diego (CA); On-site; USD 136,000 - 143,000; Full time

Job summary

PDS Defense, Inc. in San Diego, CA is seeking a Digital Engineer to design and test VHDL-based digital designs for SDR applications. You will work with FPGA tools and collaborate with multidisciplinary teams in both waterfall and Agile environments.

The role requires strong VHDL experience, formal verification knowledge, and an active Secret Clearance. Occasional collaboration with DoD systems is expected. Competitive compensation with benefits depending on assignment.

Qualifications

• BS + 5 years (MS + 3) in a STEM field.
• Hands-on VHDL design experience.
• Excellent written and communication skills; ability to work independently.
• Knowledge of formal engineering development process, VHDL design and verification.
• Active Secret Clearance required to start.

Responsibilities

• Design, develop, integrate and test VHDL-based digital designs for end-user customers, focusing on SDR VHDL firmware.
• Use FPGA programming tools and environments; collaborate with Systems, Digital, Hardware, and I&T teams.
• Work in waterfall or Agile software development environments.
• Analyze requirements and design documents to resolve functional, performance or timing issues.

Skills

VHDL design

FPGA development

Agile/Waterfall

Secret clearance

Education

BS + 5 years (MS + 3)

Tools

Vivado

Quartus

QuestaSim

Job description

PDS Defense, Inc. in San Diego, CA is seeking a Digital Engineer to design and test VHDL-based digital designs for SDR applications. You will work with FPGA tools and collaborate with multidisciplinary teams in both waterfall and Agile environments.

The role requires strong VHDL experience, formal verification knowledge, and an active Secret Clearance. Occasional collaboration with DoD systems is expected. Competitive compensation with benefits depending on assignment.