Verification Engineer IV

Mindlance; Sunnyvale (CA); Hybrid; USD 90,000 - 150,000; Full time

Job summary

An innovative company is seeking a Verification Engineer to lead the electrical system verification of cutting-edge products. In this role, you'll collaborate with researchers and engineers to define verification methodologies, create test cases, and implement testing infrastructures. Your expertise in System Verilog and UVM will be crucial as you drive the execution and reporting of verification results. This position offers the opportunity to work on state-of-the-art systems while contributing to the advancement of technology. If you're passionate about verification and enjoy hands-on coding, this role is perfect for you.

Qualifications

• 3+ years of experience with verification methodologies and languages.
• Hands-on coding skills in System Verilog and UVM.

Responsibilities

• Define electrical verification methodologies for various systems.
• Create and enhance verification environments using System Verilog and UVM.
• Communicate test plans and results clearly.

Skills

System Verilog

UVM

C#

Python

LabVIEW

Firmware Verification

Gate-Level Simulations

Low Power Verification (UPF)

Education

Bachelor's degree in Electrical Engineering

Bachelor's degree in Computer Science

Job description

Job Description:
Summary:
The main function of the Verification Engineer is to work with a group of researchers and engineers to own the electrical system level verification of ***'s products. Working closely with researchers, architects, and designers in architecting methods of electrical verification for multiple state of the art systems. Using verification skills to define verification requirements, create test cases, design and implement the testing infrastructure, execute the testing, and report the results for the new product designs.

Job Responsibilities:
• Define electrical verification methodologies for each of the different systems by working with researchers, architects, and the design teams
• Define and track detailed test plans for the different modules and top-level systems
• Define, architect, design, and drive implementation of scalable test infrastructure
• Create and enhance constraine-random verification environments using system Verilog and universal verification methodology(UVM) and track progress with coverage closure.
• Own execution, interpretation, and reporting of electrical system level verification work status and results
• Support system bring up and debug activities
• Clearly communicate test plans and results

Skills:
• Looking for a CW with hands on coding skill in SV/UVM
• Knowledge of definition of verification requirements
• Experience owning areas of product verification
• Knowledge of definition, architecture, design, and driving implementation of test automation
• Working knowledge of C#, Python, and LabVIEW
• Experience with firmware verification
• Experience in gate-level simulations and low power (UPF) verification is a plus
• Experience in silicon bring-up activities is advantageous

Education/Experience:
• Bachelors degree in Electrical Engineering, Computer Science or equivalent experience
• 3+ years of experience with Verification methodologies and languages such as UVM and System Verilog

Notes:
Onsite Sunnyvale, needs to work 3 days in person
Needs to have 3+ years of experience with Verification methodologies and languages such as UVM and System Verilog as first round will be testing for this
Please make sure these candidates are available in 3-4 weeks after offer, no delays if possible

EEO:

“Mindlance is an Equal Opportunity Employer and does not discriminate in employment on the basis of – Minority/Gender/Disability/Religion/LGBTQI/Age/Veterans.”