Transceiver Integration Architect

Altera; Chicago (IL); Remote; USD 130,000 - 180,000; Full time

Job summary

Altera is seeking a highly skilled Transceiver Integration Architect to design and integrate transceiver subsystems for their FPGA portfolio. This role involves collaboration across teams to drive technical solutions and ensure optimal performance. The ideal candidate will have extensive experience in high-speed transceiver technology and a strong educational background in Electrical Engineering.

Qualifications

• 10+ years of experience in FPGA or ASIC architecture/design.
• Deep understanding of Ethernet, PCIe, and CXL protocols.
• Track record of collaboration across technical teams.

Responsibilities

• Lead architecture of transceiver subsystems for FPGAs.
• Define SerDes requirements and collaborate with teams.
• Provide technical leadership across cross-functional teams.

Skills

SerDes technology

Protocol design

Technical leadership

Cross-functional collaboration

Education

Bachelor's or Master's degree in Electrical Engineering

Job description

Transceiver Integration Architect page is loaded

Transceiver Integration Architect

Apply locations Arizona, United States (Remote) San Jose, California, United States time type Full time posted on Posted 3 Days Ago job requisition id R00892

Job Details:

Job Description:

We are seeking a highly skilled and experienced Transceiver (XCVR) Integration Architect to lead the definition and architecture of transceiver subsystems for Altera’s FPGA portfolio. This individual will drive the selection and integration of SerDes (Serializer/Deserializer) and Layer 2+ IP stacks (e.g., Ethernet, PCIe) to support scalable FPGA solutions across low, mid, and high-performance products.

Key Responsibilities

• Architect transceiver subsystems for Altera FPGAs, including selection and integration of SerDes and Layer 2+ protocols such as Ethernet and PCIe.

• Define SerDes requirements in collaboration with the SerDes team; co-architect end-to-end solutions that balance protocol support, integration complexity, and usability for FPGA applications.

• Serve as the technical interface between the SerDes team and broader design, integration, and system engineering teams.

• Define integration requirements for building complete subsystems with IP, bridges, reset logic, and power plans optimized for usability, performance, and power efficiency.

• Partner with soft IP and software teams to ensure seamless integration and a smooth user experience for end customers.

• Monitor and analyze industry trends, customer requirements, and evolving standards to guide product direction and architecture strategies.

• Provide technical leadership across cross-functional teams including validation, verification, packaging, software, planning, and product marketing.

• Represent Altera in customer and industry engagements, helping to shape future FPGA capabilities based on market feedback.

Qualifications:

Minimum Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

• 10+ years of experience in FPGA or ASIC architecture/design with a focus on high-speed transceivers and protocol IP integration.

Preferred Qualifications:

• Deep understanding of SerDes technology, protocols (Ethernet, PCIe, CXL, etc.), and transceiver subsystem architecture.

• Experience defining and integrating soft and hard IP within FPGA environments.

• Knowledge of power management strategies, IP interface design, reset architecture, and software interaction models.

• Proven track record of technical leadership and cross-functional collaboration.

• Strong communication skills and ability to influence product direction at a senior level.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

Arizona, United States (Remote)

Additional Locations:

San Jose, California, United States

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Ourend-to-endbroad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.

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